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TLK2521IPAPG4 Datasheet(PDF) 4 Page - Texas Instruments |
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TLK2521IPAPG4 Datasheet(HTML) 4 Page - Texas Instruments |
4 / 22 page TLK2521 1.0 to 2.5 Gbps 18BIT SERDES SLLS574D − JULY 2003 − REVISED JULY 2007 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 GTX_CLK TXDn tsu th Figure 1. Transmit Timing Waveform transmission latency The data transmission latency of the TLK2521 is defined as the delay from the initial 18-bit word load to the serial transmission of bit 0. The transmit latency is fixed once the link is established. However, due to silicon process variations and implementation variables such as supply voltage and temperature, the exact delay varies slightly. Figure 2 illustrates the timing relationship between the transmit data bus, GTX_CLK, and serial transmit pins. Detailed latency information can be found in the transmitter/receiver characteristics table. 16-Bit Word to Transmit Transmitted 20-Bit Word DOUTTXP, DOUTTXN TXD(0−17) GTX_CLK td(Tx latency) Figure 2. Transmitter Latency start/stop framing logic All true serial interfaces require a method of encoding to insure minimum transition density so that the receiving PLL has a minimal number of transitions in which to stay locked onto the data stream. The signal coding also provides a mechanism for the receiver to identify the byte boundary for correct deserialization. The TLK2521 wraps a start bit (1) and a stop bit (0) around the 18-bit data payload as shown in Figure 3. This is transparent to the user as the TLK2521 internally adds the framing bits to the data such that the user reads and writes actual 18-bit data. start/stop framing logic (continued) ... Start Bit Stop Bit TD0 TD1 TD16 TD17 Start Bit Stop Bit Figure 3. Serial Output Data Stream with Start and Stop Bit |
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