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LNK606PG Datasheet(PDF) 6 Page - Power Integrations, Inc. |
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LNK606PG Datasheet(HTML) 6 Page - Power Integrations, Inc. |
6 / 18 page Rev. F 01/10 6 LNK603-606/613-616 www.powerint.com Secondary Loop Area To minimize leakage inductance and EMI the area of the loop connecting the secondary winding, the output diode and the output filter capacitor should be minimized. In addition, sufficient copper area should be provided at the anode and cathode terminal of the diode for heatsinking. A larger area is preferred at the quiet cathode terminal. A large anode area can increase high frequency radiated EMI. Electrostatic Discharge Spark Gap An trace is placed along the isolation barrier to form one electrode of a spark gap. The other electrode on the secondary is formed by the output return node. The spark gap directs ESD energy from the secondary back to the AC input. The trace from the AC input to the spark gap electrode should be spaced away from other traces to prevent unwanted arcing occurring and possible circuit damage. Drain Clamp Optimization LinkSwitch-II senses the feedback winding on the primary side to regulate the output. The voltage that appears on the feed- back winding is a reflection of the secondary winding voltage while the internal MOSFET is off. Therefore any leakage inductance induced ringing can affect output regulation. Optimizing the drain clamp to minimize the high frequency ringing will give the best regulation. Figure 6 shows the desired drain voltage waveform compared to Figure 7 with a large undershoot due to the leakage inductance induced ring. This will reduce the output voltage regulation performance. To reduce this adjust the value of the resistor in series with the clamp diode. Figure 5. PCB Layout Example Showing 5.1 W Design Using P Package. Addition of a Bias Circuit for Higher Light Load Efficiency and Lower No-load Input Power Consumption. The addition of a bias circuit can decrease the no-load input power from ~200 mW down to less than 30 mW at 230 VAC input. Light load efficiency also increases which may avoid the need to use a Schottky barrier vs PN junction output diode while still meeting average efficiency requirements. The power supply schematic shown in Figure 4 has the bias circuit incorporated. Diode D6, C5 and R4 form the bias circuit. As the output voltage is less than 8 V, an additional transformer winding is needed, AC stacked on top of the feedback winding. This provides a high enough voltage to supply the BYPASS pin even during low switching frequency operation at no-load. In Figure 4 the additional bias winding (from pin 2 to pin 1) is stacked on top of the feedback winding (pin 4 to pin 2). Diode D6 rectifies the output and C5 is the filter capacitor. A 10 uF capacitor is recommended to hold up the bias voltage at low switching frequencies. The capacitor type is not critical but the voltage rating should be above the maximum value of V BIAS. The recommended current into the BYPASS pin is equal to IC supply current (~0.5 mA) at the minimum bias winding voltage. The BYPASS pin current should not exceed 3 mA at the maximum bias winding voltage. The value of R4 is calculated according to (V BIAS – VBP)/IS2, where VBIAS (10 V typ.) is the voltage across C5, IS2 (0.5 mA typ.) is the IC supply current and V BP (6.2 V typ.) is the DC Output PI-5110-050508 R5 C4 C5 C3 R4 D5 D3 R3 R1 C2 R1 C1 R6 R2 L2 D4 D2 D1 U1 D3 RF1 D7 T1 R8 C6 C7 C8 R9 Output Filter Capacitors Input Stage Primary Clamp Output Diode Snubber Preload Resistor Spark Gap Bypass Capacitor Feedback Resistors Bypass Supply Components AC Input S S S S BP D FB LinkSwitch-II |
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