FAN5093

PRODUCT SPECIFICATION

2

REV. 1.1.0 3/27/03

Pin Assignments

Pin Definitions

Pin Number

Pin Name

Pin Function Description

1-5

VID0-4

Voltage Identification Code Inputs. Open collector/TTL compatible inputs will

program the output voltage over the ranges specified in Table 1. Internally Pulled-

Up.

6

BYPASS

5V Rail. Bypass this pin with a 0.1

µF ceramic capacitor to AGND.

7

AGND

Analog Ground. Return path for low power analog circuitry. This pin should be

connected to a low impedance system ground plane to minimize ground loops.

8

LDRVB

Low Side FET Driver for B. Connect this pin to the gate of an N-channel

MOSFET for synchronous operation. The trace from this pin to the MOSFET gate

should optimally be <0.5".

9

PGNDB

Power Ground B. Return pin for high currents flowing in low-side MOSFET.

Connect directly to low-side MOSFET source.

10

SWB

High side driver source and low side driver drain switching node B. Gate

drive return for high side MOSFET, and negative input for low-side MOSFET

current sense.

11

HDRVB

High Side FET Driver B. Connect this pin to the gate of an N-channel MOSFET.

The trace from this pin to the MOSFET gate should optimally be <0.5".

12

BOOTB

Bootstrap B. Input supply for high-side MOSFET.

13

BOOTA

Bootstrap A. Input supply for high-side MOSFET.

14

HDRVA

High Side FET Driver A. Connect this pin to the gate of an N-channel MOSFET.

The trace from this pin to the MOSFET gate should optimally be <0.5".

15

SWA

High side driver source and low side driver drain switching node A. Gate

drive return for high side MOSFET, and negative input for low-side MOSFET

current sense.

16

PGNDA

Power Ground A. Return pin for high currents flowing in low-side MOSFET.

Connect directly to low-side MOSFET source.

17

LDRVA

Low Side FET Driver for A. Connect this pin to the gate of an N-channel

MOSFET for synchronous operation. The trace from this pin to the MOSFET gate

should optimally be <0.5".

18

VCC

VCC. Internal IC supply. Connect to system 12V supply, and decouple with a 10

Ω

resistor and 1

µF ceramic capacitor.

19

PWRGD

Power Good Flag. An open collector output that will be logic LOW if the output

voltage is less than 350mV less than the nominal output voltage setpoint. Power

Good is prevented from going low until the output voltage is out of spec for

500µsec.

FAN5093

VID0

VID1

VID2

VID3

VID4

AGND

BYPASS

LDRVB

PGNDB

SWB

HDRVB

BOOTB

VFB

RT

ENABLE/SS

DROOP/E*

ILIM

PWRGD

VCC

LDRVA

PGNDA

SWA

HDRVA

BOOTA

1

2

3

4

5

6

7

8

9

10

11

12

24

23

22

21

20

19

18

17

16

15

14

13