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EVAL-SDP-CB1Z Datasheet(PDF) 10 Page - Analog Devices |
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EVAL-SDP-CB1Z Datasheet(HTML) 10 Page - Analog Devices |
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10 / 20 page  AD7091 Data Sheet Rev. A | Page 10 of 20 THEORY OF OPERATION CIRCUIT INFORMATION The AD7091 is a 12-bit successive approximation register analog-to-digital converter (SAR ADC) that offers ultralow power consumption (typically 367 µA at 3 V and 1 MSPS) while achieving fast throughput rates (1 MSPS with a 50 MHz SCLK). The part operates from a single power supply in the range of 2.09 V to 5.25 V. The AD7091 provides an on-chip track-and-hold amplifier and an analog-to-digital converter (ADC) with a serial interface housed in a tiny 8-lead LFCSP package. This package offers considerable space-saving advantages compared with alternative solutions. The serial clock input accesses data from the part. The clock for the SAR ADC is generated internally. The analog input range is 0 V to VDD. An external reference is not required for the ADC, nor is there a reference on chip. The reference voltage for the AD7091 is derived from the power supply and, thus, provides the widest dynamic input range of 0 V to VDD. The AD7091 also features a power-down option to save power between conversions. The power-down feature is implemented using the standard serial interface, as described in the Modes of Operation section. CONVERTER OPERATION The AD7091 is a SAR ADC based around a charge redistribu- tion DAC. Figure 15 and Figure 16 show simplified schematics of the ADC. Figure 15 shows the ADC during its acquisition phase; SW2 is closed and SW1 is in Position A. The comparator is held in a balanced condition, and the sampling capacitor acquires the signal on VIN. CHARGE REDISTRIBUTION DAC CONTROL LOGIC COMPARATOR SW2 SAMPLING CAPACITOR ACQUISITION PHASE SW1 A B GND LDO/2 VIN Figure 15. ADC Acquisition Phase When the ADC starts a conversion, SW2 opens and SW1 moves to Position B, causing the comparator to become unbalanced (see Figure 16). The control logic and the charge redistribution DAC are used to add and subtract fixed amounts of charge from the sampling capacitor to bring the comparator back into a balanced condition. When the comparator is rebalanced, the conversion is complete. The control logic generates the ADC output code. Figure 17 shows the ADC transfer function. CHARGE REDISTRIBUTION DAC CONTROL LOGIC COMPARATOR SW2 SAMPLING CAPACITOR CONVERSION PHASE SW1 A B GND LDO/2 VIN Figure 16. ADC Conversion Phase ADC TRANSFER FUNCTION The output coding of the AD7091 is straight binary. The designed code transitions occur midway between successive integer LSB values, such as 0.5 LSB, 1.5 LSB, and so on. The LSB size for the AD7091 is VDD/4096. The ideal transfer characteristic for the AD7091 is shown in Figure 17. 000 ... 000 0V ANALOG INPUT 111 ... 111 000 ... 001 000 ... 010 111 ... 110 111 ... 000 011 ... 111 1LSB VDD – 1LSB 1LSB = VDD /4096 Figure 17. AD7091 Transfer Characteristic |
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