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BF1202WR Datasheet(PDF) 8 Page - NXP Semiconductors |
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BF1202WR Datasheet(HTML) 8 Page - NXP Semiconductors |
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8 / 15 page  2010 Sep 16 8 NXP Semiconductors Product specification N-channel dual-gate PoLo MOS-FETs BF1202; BF1202R; BF1202WR handbook, halfpage MCD964 10 f (GHz) Yis (mS) 102 103 102 10 1 10−1 bis gis Fig.17 Input admittance as a function of frequency; typical values. VDS =5 V; VG2 =4 V. ID =12mA; Tamb =25 C. handbook, halfpage MCD965 10 f (MHz) 102 103 103 102 10 1 −103 −102 −10 −1 yrs ( μS) ϕrs (deg) ϕrs yrs Fig.18 Reverse transfer admittance and phase as a function of frequency; typical values. VDS =5 V; VG2 =4 V. ID =12mA; Tamb =25 C. handbook, halfpage 102 10 1 −102 −10 −1 MCD966 10 102 103 f (MHz) yfs (mS) ϕfs (deg) yfs ϕfs Fig.19 Forward transfer admittance and phase as a function of frequency; typical values. VDS =5 V; VG2 =4 V. ID =12mA; Tamb =25 C. handbook, halfpage MCD967 10 bos f (MHz) Yos (mS) 102 103 10 1 10−2 10−1 gos Fig.20 Output admittance as a function of frequency; typical values. VDS =5 V; VG2 =4 V. ID =12mA; Tamb =25 C. |
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