1

Rev. 00B

10/15/2012

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IS61LF204836B, IS61VF/VVF204836B

IS61LF409618B, IS61VF/VVF409618B

FEATURES

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Burst sequence control using MODE input

• Three chip enable option for simple depth expan-

sion and address pipelining

• Common data inputs and data outputs

• Auto Power-down during deselect

• Single cycle deselect

• Snooze MODE for reduced-power standby

• JTAG Boundary Scan for PBGA package

• Power Supply

• JEDEC 100-Pin TQFP, 119-pin PBGA, and 165-

pin PBGA packages

• Lead-free available

ADVANCED INFORMATION

OCTOBER 2012

2M x 36, 4M x 18

72 Mb SYNCHRONOUS FLOW-THROUGH

STATIC RAM

DESCRIPTION

The 72Mb product family features high-speed, low-power

synchronous static RAMs designed to provide burstable,

high-performance memory for communication and network-

ing applications. The IS61LF/VF204836B is organized as

2,096,952 words by 36 bits. The IS61LF/VF409618B is

organized as 4,193,904 words by 18 bits. Fabricated with

a 2-bit burst counter, high-speed SRAM core, and high-

drive capability outputs into a single monolithic circuit. All

synchronous inputs pass through registers controlled by

a positive-edge-triggered single clock input.

Writecyclesareinternallyself-timedandareinitiatedbythe

rising edge of the clock input. Write cycles can be one to

four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be writ-

ten. Byte write operation is performed by using byte write

enable (BWE) input combined with one or more individual

byte write signals (BWx). In addition, Global Write (GW)

is available for writing all bytes at one time, regardless of

the byte write controls.

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller)

input pins. Subsequent burst addresses can be gener-

ated internally and controlled by the ADV (burst address

advance) input pin.

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW. Inter-

leave burst is achieved when this pin is tied HIGH or left

floating.

FAST ACCESS TIME

Symbol

Parameter

-6.5

-7.5

Units

Clock Access Time

6.5

7.5

ns

Cycle Time

7.5

8.5

ns

Frequency

133

117

MHz