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A3PN020Z2VQ100ES Datasheet(PDF) 10 Page - Microsemi Corporation |
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A3PN020Z2VQ100ES Datasheet(HTML) 10 Page - Microsemi Corporation |
10 / 114 page ProASIC3 nano Device Overview 1-4 Revision 11 The FPGA core consists of a sea of VersaTiles. Each VersaTile can be configured as a three-input logic function, a D-flip-flop (with or without enable), or a latch by programming the appropriate flash switch interconnections. The versatility of the ProASIC3 nano core tile as either a three-input lookup table (LUT) equivalent or as a D-flip-flop/latch with enable allows for efficient use of the FPGA fabric. The VersaTile capability is unique to the ProASIC3 family of third-generation architecture flash FPGAs. VersaTiles are connected with any of the four levels of routing hierarchy. Flash switches are distributed throughout the device to provide nonvolatile, reconfigurable interconnect programming. Maximum core utilization is possible for virtually any design. Figure 1-3 • ProASIC3 nano Device Architecture Overview with Two I/O Banks (A3PN060 and A3PN125) Figure 1-4 • ProASIC3 nano Device Architecture Overview with Four I/O Banks (A3PN250) RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block VersaTile CCC I/Os ISP AES Decryption User Nonvolatile FlashROM Charge Pumps Bank 0 Bank 1 RAM Block 4,608-Bit Dual-Port SRAM or FIFO Block VersaTile CCC I/Os ISP AES Decryption User Nonvolatile FlashROM Charge Pumps Bank 0 Bank 2 |
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