6

Rev. A

11/11/02

IS61NF12832

IS61NF12836

IS61NF25618

IS61NLF12832

IS61NLF12836

IS61NLF25618

Address

Operation

Used

CS

CS

CS

CS

CS1

CS2

CS

CS

CS

CS

CS2

ADV

WE

WE

WE

WE

WE

BW

BW

BW

BW

BWx

OE

OE

OE

OE

OE

CKE

CKE

CKE

CKE

CKE

CLK

Not Selected Continue

N/A

X

X

X

H

X

X

X

L

↑

Begin Burst Read

External Address

L

H

L

L

H

X

L

L

↑

Continue Burst Read

Next Address

X

X

X

H

X

X

L

L

↑

NOP/Dummy Read

External Address

L

H

L

L

H

X

H

L

↑

Dummy Read

Next Address

X

X

X

H

X

X

H

L

↑

Begin Burst Write

External Address

L

H

L

L

L

L

X

L

↑

Continue Burst Write

Next Address

X

X

X

H

X

L

X

L

↑

NOP/Write Abort

N/A

L

H

L

L

L

H

X

L

↑

Write Abort

Next Address

X

X

X

H

X

H

X

L

↑

Ignore Clock

Current Address

X

X

X

X

X

X

X

H

↑

Notes:

1. "X" means don't care.

2. The rising edge of clock is symbolized by

↑

3. A continue deselect cycle can only be entered if a deselect cycle is executed first.

4.

WE = L means Write operation in Write Truth Table.

WE = H means Read operation in Write Truth Table.

5. Operation finally depends on status of asynchronous pins (ZZ and

OE).

BURST

READ

DESELECT

BURST

WRITE

BEGIN

READ

BEGIN

WRITE

READ

WRITE

READ

WRITE

BURST

BURST

BURST

DS

DS

DS

READ

DS

DS

READ

WRITE

WRITE

BURST

BURST

WRITE

READ

STATE DIAGRAM