IS43/46DR86400B, IS43/46DR16320B

Integrated Silicon Solution, Inc. – www.issi.com –

2

Rev. I, 8/01/2012

Package Ball-out and Description

DDR2 SDRAM (64Mx8) 60-ball TW-BGA Ball-out (Top-View) (10.00 mm X 10.50 mm Body, 0.8 mm pitch)

Description

Input clocks

Clock enable

Chip Select

Command control pins

Address

Bank Address

I/O

Data Strobe

Redundant Data Strobe

Input data mask

Supply voltage

Ground

DQ power supply

DQ ground

Reference voltage

DLL power supply

DLL ground

On Die Termination Enable

No connect

Symbol

CK, CK#

CKE

CS#

RAS#,CAS#,WE#

A[13:0]

BA[1:0]

DQ[7:0]

DQS, DQS#

RDQS, RDQS#

DM

VDD

VDDL

VSSDL

NC

VSS

VDDQ

VSSQ

VREF

ODT

Notes:

1. Pins B3 and A2 have identical capacitance as pins B7

and A8.

2. For a read, when enabled, strobe pair RDQS & RDQS#

are identical in function and timing to strobe pair DQS &

DQS# and input masking function is disabled.

3. The function of DM or RDQS/RDQS# are enabled by

EMRS command.

4. VDDL and VSSDL are power and ground for the DLL.