1

Rev. A

11/11/02

IS61NF12832

IS61NF12836

IS61NF25618

IS61NLF12832 IS61NLF12836 IS61NLF25618

ISSI reserves the right to make changes this specification herein and it products at any time without notice. ISSI assumes no responsibility or liability arising out of the application or use of any information,

product or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders for products.

© Copyright 2000, Integrated Silicon Solution, Inc

FEATURES

• 100 percent bus utilization

• No wait cycles between Read and Write

• Internal self-timed write cycle

• Individual Byte Write Control

• Single R/W (Read/Write) control pin

• Clock controlled, registered address,

data and control

• Interleaved or linear burst sequence control

using MODE input

• Three chip enables for simple depth expansion

and address pipelining for TQFP

• Power Down mode

• Common data inputs and data outputs

•

CKE pin to enable clock and suspend operation

• JEDEC 100-pin TQFP, 119 PBGA package

• Single +3.3V power supply (± 5%)

• NF Version: 3.3V I/O Supply Voltage

• NLF Version: 2.5V I/O Supply Voltage

• Industrial temperature available

DESCRIPTION

The 4 Meg 'NF' product family feature high-speed,

low-power synchronous static RAMs designed to provide

a burstable, high-performance, 'no wait' state, device for

network and communications customers. They are

organized as 131,072 words by 32 bits, 131,072 words

by 36 bits and 262,144 words by 18 bits, fabricated with

Incorporating a 'no wait' state feature, wait cycles are

eliminated when the bus switches from read to write, or

write to read. This device integrates a 2-bit burst counter,

high-speed SRAM core, and high-drive capability outputs

into a single monolithic circuit.

All synchronous inputs pass through registers are controlled

by a positive-edge-triggered single clock input. Operations

may be suspended and all synchronous inputs ignored

when Clock Enable,

CKE is HIGH. In this state the internal

device will hold their previous values.

All Read, Write and Deselect cycles are initiated by the

ADV input. When the ADV is HIGH the internal burst

counter is incremented. New external addresses can be

loaded when ADV is LOW.

Write cycles are internally self-timed and are initiated by

the rising edge of the clock inputs and when

WE is LOW.

Separate byte enables allow individual bytes to be written.

A burst mode pin (MODE) defines the order of the burst

sequence. When tied HIGH, the interleaved burst sequence

is selected. When tied LOW, the linear burst sequence is

selected.

128K x 32, 128K x 36 and 256K x 18

FLOW-THROUGH 'NO WAIT' STATE BUS

SRAM

NOVEMBER 2002

FAST ACCESS TIME

Symbol

Parameter

-8.5

-9

-10

Units

Clock Access Time

8.5

9

10

ns

Cycle Time

10

12

12

ns

Frequency

100

83

83

MHz