Integrated Silicon Solution, Inc. — www.issi.com

1

Rev. D

06/19/2013

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est version of this device specification before relying on any published information and before placing orders for products.

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IS62WV25616DALL/DBLL, IS65WV25616DBLL

256K x 16 LOW VOLTAGE,

ULTRA LOW POWER CMOS STATIC SRAM

FEATURES

• High-speed access time: 35, 45, 55 ns

• CMOSlowpoweroperation

30 mW (typical) operating

6µW(typical)CMOSstandby

• TTLcompatibleinterfacelevels

• Singlepowersupply

• Fullystaticoperation:noclockorrefresh

required

• Threestateoutputs

• Datacontrolforupperandlowerbytes

• IndustrialandAutomotivetemperaturesupport

• Lead-freeavailable

• 2CSoptionavailable

DESCRIPTION

The

arehigh-speed,lowpower,4MbitSRAMsorganizedas

256K words by 16 bits. It is fabricated using

performanceCMOStechnology.Thishighlyreliableprocess

coupled with innovative circuit design techniques, yields

high-performance and low power consumption devices.

When CS1 is HIGH (deselected) or when CS2 is LOW

(deselcted) or when CS1isLOW,CS2isHIGHandboth

LB

and UB are HIGH, the device assumes a standby mode

at which the power dissipation can be reduced down with

CMOSinputlevels.

Easy memory expansion is provided by using Chip Enable

andOutputEnableinputs.TheactiveLOWWriteEnable(WE)

controls both writing and reading of the memory.A data byte

allows Upper Byte (UB)andLowerByte(LB) access.

TheIS62WV25616DALLandIS62/65WV25616DBLLare

packaged in the JEDEC standard 44-PinTSOP(TYPEII)

and 48-pin mini BGA (6mmx8mm).

FUNCTIONAL BLOCK DIAGRAM

JUNE 2013

A0-A17

CS1

CS2

OE

WE

256K x 16

MEMORY ARRAY

DECODER

COLUMN I/O

CONTROL

CIRCUIT

GND

I/O

DATA

CIRCUIT

I/O0-I/O7

Lower Byte

I/O8-I/O15

Upper Byte

UB

LB