Advanced Power

Electronics Corp.

APE6809_6812

APPLICATION INFORMATION

Ensuring a Valid Reset Output Down to VCC = 0

Ensuring a Valid Reset Output Down to VCC = 0

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RESET is guaranteed to be a logic low for VCC > 1.0V. Once VCC exceeds the

reset threshold, an internal timer keeps RESET low for the reset timeout period; after

this interval, RESET goes high. If a brownout condition occurs (VCC dips below the

reset threshold), RESET goes low. Any time VCC goes below the reset threshold, the

internal timer resets to zero, and RESET goes low. The internal timer starts after VCC

returns above the reset threshold, and RESET remains low for the reset timeout

period.

When VCC falls below 1.0V, the APE6809/APE6811 RESET output no longer sinks

current—it becomes an open circuit. Therefore, high-impedance CMOS logic inputs

connected to RESET can drift to undetermined voltages.

This presents no problem in most applications since most µP and other circuitry is

inoperative with VCC below 1.0V. However, in applications where RESET must be

valid down to 0V, adding a pull down resistor to causes any stray leakage currents to

flow to ground, holding RESET low. R1’s value is not critical; 100k is large enough not

to load RESET and small enough to pull RESET to ground. For the

APE6810/APE6812 if RESET is required to remain valid for VCC < 1.0V.

Most µP supervisor ICs has reset threshold voltages between 5% and 10%

below the value of nominal supply voltages. This ensures a reset will not occur within

5% of the nominal supply, but will occur when the supply is 10% below nominal. When

using ICs rated at only the nominal supply ±5%, this leaves a zone of uncertainty

where the supply is between 5% and 10% low, and where the reset may or may not be

asserted.