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AD7862 Datasheet(PDF) 10 Page - Analog Devices |
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AD7862 Datasheet(HTML) 10 Page - Analog Devices |
10 / 16 page AD7862 –10– REV. 0 respectively). The third and fourth read pulses, after the second conversion and A0 high, access the result from Channel B (VB1 and VB2 respectively). Data is read from the part via a 12-bit parallel data bus with standard CS and RD signals. This data read operation consists of negative going pulse on the CS pin combined with a negative going pulse on the RD pin; this repeated twice will access the two 12-bit results. For the fastest throughput rate (with an internal clock of 3.7 MHz), the read operation will take 100 ns. The read operation must be complete at least 300 ns before the falling edge of the next CONVST, and this gives a total time of 4 µs for the full throughput time (equivalent to 250 kHz). This mode of operation should be used for high sampling applications. Mode 2 Operation (Auto Sleep After Conversion) The timing diagram in Figure 6 is for optimum performance in Operating Mode 2 where the part automatically goes into sleep mode once BUSY goes low after conversion and “wakes-up” before the next conversion takes place. This is achieved by keeping CONVST low at the end of the second conversion, whereas it was high at the end of the second conversion for Mode 1 opera- tion. The operation shown in Figure 6 shows how to access data from both Channels A and B followed by the Auto Sleep mode. One can also setup the timing to access data from Channel A only or Channel B only (see Read Options section on previous page) and then go into Auto-Sleep mode. The rising edge of CONVST “wakes-up” the part. This wake-up time is 2.5 µs when using an external reference and 5 ms when using the internal reference at which point the Track/Hold amplifier’s go into their hold mode, provided the CONVST has gone low. The conversion takes 3.6 µs after this, giving a total of 6 µs (external reference, 5.0035 ms for internal reference) from the rising edge of CONVST to the conversion being complete, which is indicated by the BUSY going low. Note that since the wake-up time from the rising edge of CONVST is 2.5 µs, if the CONVST pulse width is greater than 2.5 µs, the conversion will take more than the 6 µs (2.5 µs wake-up time + 3.6 µs conversion time) shown in the diagram from the rising edge of CONVST. This is because the track/hold amplifiers go into their hold mode on the falling edge of CONVST, and the conversion will not be complete for a further 3.6 µs. In this case the BUSY will be the best indicator for when the conversion is complete. Even though the part is in sleep mode, data can still be read from the part. The read operation is identical to Mode 1 operation and must also be complete at least 300 ns before the falling edge of the next CONVST to allow the track/hold amplifiers to have enough time to settle. This mode is very useful when the part is convert- ing at a slow rate, as the power consumption will be significantly reduced from that of Mode 1 operation. DYNAMIC SPECIFICATIONS The AD7862 is specified and 100% tested for dynamic perfor- mance specifications as well as traditional dc specifications such as Integral and Differential Nonlinearity. These ac specifications are required for the signal processing applications such as phased array sonar, adaptive filters and spectrum analysis. These applica- tions require information on the ADC’s effect on the spectral content of the input signal. Hence, the parameters for which the AD7862 is specified include SNR, harmonic distortion, inter- modulation distortion and peak harmonics. These terms are discussed in more detail in the following sections. Signal-to-Noise Ratio (SNR) SNR is the measured signal-to-noise ratio at the output of the ADC. The signal is the rms magnitude of the fundamental. Noise is the rms sum of all the nonfundamental signals up to half the sampling frequency (fS/2) excluding dc. SNR is depen- dent upon the number of quantization levels used in the digitization process; the more levels, the smaller the quantiza- tion noise. The theoretical signal to noise ratio for a sine wave input is given by SNR = (6.02N + 1.76) dB (1) where N is the number of bits. Thus for an ideal 12-bit converter, SNR = 74 dB. VA1 VA2 VB1 VB2 t 3 t CONV = 3.6µs CONVST BUSY A0 CS RD DATA 300ns 400ns t 3 2.5µs*/5ms** WAKE-UP TIME t CONV = 3.5µs **WHEN USING AN EXTERNAL REFERENCE, WAKE-UP TIME = 2.5µs **WHEN USING AN INTERNAL REFERENCE, WAKE-UP TIME = 5ms Figure 6. Mode 2 Timing Where Automatic Sleep Function Is Initiated |
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