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A3PN125ZQNG100PP Datasheet(PDF) 9 Page - Microsemi Corporation |
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A3PN125ZQNG100PP Datasheet(HTML) 9 Page - Microsemi Corporation |
9 / 114 page ProASIC3 nano Flash FPGAs Revision 11 1-3 Advanced Architecture The proprietary ProASIC3 nano architecture provides granularity comparable to standard-cell ASICs. The ProASIC3 nano device consists of five distinct and programmable architectural features (Figure 1-3 to Figure 1-4 on page 1-4): • FPGA VersaTiles • Dedicated FlashROM • Dedicated SRAM/FIFO memory • Extensive CCCs and PLLs • Advanced I/O structure Note: *Bank 0 for the A3PN030 device Figure 1-1 • ProASIC3 Device Architecture Overview with Two I/O Banks and No RAM (A3PN010 and A3PN030) Figure 1-2 • ProASIC3 nano Architecture Overview with Three I/O Banks and No RAM (A3PN015 and A3PN020) VersaTile I/Os User Nonvolatile FlashROM Charge Pumps Bank 1* Bank 1 CCC-GL VersaTile I/Os User Nonvolatile FlashROM Charge Pumps Bank 1 Bank 1 CCC-GL |
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