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dsPIC33FJ06GS102 Datasheet(PDF) 9 Page - Microchip Technology |
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dsPIC33FJ06GS102 Datasheet(HTML) 9 Page - Microchip Technology |
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9 / 20 page  2009-2013 Microchip Technology Inc. DS80439M-page 9 dsPIC33FJ06GS101/X02 and dsPIC33FJ16GSX02/X04 18. Module: PGEC3/PGED3 Programming Pins When using the PGEC3/PGED3 pins for device programming, the programming time may be slower as compared to other available PGECx/ PGEDx pin pairs, because the Enhanced ICSP™ programming algorithm cannot be executed on this pin pair. Refer to the “dsPIC33F/PIC24H Flash Programming Specification” (DS70152) for additional information on this limitation. Work around Use alternate PGECx/PGEDx programming pin pairs. Affected Silicon Revisions 19. Module: UART The UART module will not generate consecutive Break characters. Trying to perform a back-to- back Break character transmission will cause the UART module to transmit the dummy character used to generate the first Break character instead of transmitting the second Break character. Break characters are generated correctly if they are followed by non-Break character transmission. Work around None. Affected Silicon Revisions 20. Module: PWM Cycle-by-cycle current-limit operation does not work when the PWM module is configured for Center-Aligned mode. Work around None. Affected Silicon Revisions 21. Module: PWM During normal operation, if Leading-Edge Blanking (LEB) is triggered to start counting at a rising edge of PWM and the PWM module has a blanking time period less than the PWM assertive time (TON time), and the current-limit event occurs during the TON period and is still pending after the TON period is over, the current-limit event should be ignored during TON time, but should be recognized after the TON time is over. However, the device fails to recognize the current- limit event after TON time is over, when previously described conditions exist. Work around Initialize the LEBCONx register as shown below, which specifies the LEB function for the (CLSRC) input to be triggered on the falling (trailing) edge of PWM, and set the LEB delay to a minimum value of 8 ns: • PHF bit is set • CLLEBEN bit is set • LEB<9:3> bits are set to a minimum value of ‘1’ If the user application needs LEB to be triggered at a falling edge, make sure that the LEB delay is set for more than the TON time. Affected Silicon Revisions 22. Module: UART When the UART is operating in 8-bit mode (PDSEL = 0x) and using the IrDA® encoder/ decoder (IREN = 1), the module incorrectly transmits a data payload of 80h as 00h. Work around None. Affected Silicon Revisions A2 A3 A4 XX X A2 A3 A4 XX X A2 A3 A4 XX X A2 A3 A4 XX X A2 A3 A4 XX X |
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