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C8051F852-B-GM Datasheet(PDF) 10 Page - Silicon Laboratories |
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C8051F852-B-GM Datasheet(HTML) 10 Page - Silicon Laboratories |
10 / 290 page C8051F85x/86x 10 Preliminary Rev 0.6 Table 1.3. Reset and Supply Monitor Parameter Symbol Test Condition Min Typ Max Unit VDD Supply Monitor Threshold VVDDM 1.85 1.95 2.1 V Power-On Reset (POR) Threshold VPOR Rising Voltage on VDD — 1.4 — V Falling Voltage on VDD 0.8 — 1.3 V VDD Ramp Time tRMP Time to VDD > 2.2 V 10 — 3000 µs Reset Delay from POR tPOR Relative to VDD > VPOR 3 — TBD ms Reset Delay from non-POR source tRST Time between release of reset source and code execution — 30 — µs RST Low Time to Generate Reset tRSTL 15 — — µs Missing Clock Detector Response Time (final rising edge to reset) tMCD FSYSCLK > 1 MHz — 0.625 1.2 ms Missing Clock Detector Trigger Frequency FMCD — 7.5 13 kHz VDD Supply Monitor Turn-On Time tMON — 2 — µs Table 1.4. Flash Memory Parameter Symbol Test Condition Min Typ Max Units Write Time1 tWRITE One Byte TBD 20 TBD µs Erase Time1 tERASE One Page TBD 5 TBD ms VDD Voltage During Programming2 VPROG 2.2 — 3.6 V Endurance (Write/Erase Cycles) NWE 20k 100k — Cycles Notes: 1. Does not include sequencing time before and after the write/erase operation, which may be multiple SYSCLK cycles. 2. Flash can be safely programmed at any voltage above the supply monitor threshold (VVDDM). 3. Data Retention Information is published in the Quarterly Quality and Reliability Report. |
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