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ADDI7100BCPZRL Datasheet(PDF) 5 Page - Analog Devices |
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ADDI7100BCPZRL Datasheet(HTML) 5 Page - Analog Devices |
5 / 20 page ADDI7100 Rev. C | Page 5 of 20 TIMING SPECIFICATIONS CL = 20 pF, fSAMP = 45 MHz, unless otherwise noted. See Figure 3, Figure 4, and Figure 16. Table 4. Parameter Symbol Min Typ Max Unit SAMPLE CLOCKS DATACLK, SHP, SHD Clock Period tCONV 22 ns DATACLK High/Low Pulse Width tADC 9 11 ns SHP Pulse Width tSHP 5.5 ns SHD Pulse Width tSHD 5.5 ns CLPOB Pulse Width1 2 20 Pixels SHP Rising Edge to SHD Falling Edge tS3 5.5 ns SHP Rising Edge to SHD Rising Edge tS1 9 11 tCONV − tS2 ns SHD Rising Edge to SHP Rising Edge tS2 9 11 tCONV − tS1 ns SHD Rising Edge to SHP Falling Edge tS4 5.5 ns Internal Clock Delay tID 4 ns DATA OUTPUTS Output Delay tOD 15 ns Pipeline Delay 15 Cycles SERIAL INTERFACE Maximum SCK Frequency (Must Not Exceed Pixel Rate) fSCLK 40 MHz SL to SCK Setup Time tLS 10 ns SCK to SL Hold Time tLH 10 ns SDATA Valid to SCK Rising Edge Setup tDS 10 ns SCK Rising Edge to SDATA Valid Hold tDH 10 ns 1 Minimum CLPOB pulse width is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp performance. Timing Diagrams PIXEL N PIXEL N + 1 PIXEL N + 2 PIXEL N + 14 PIXEL N + 15 tOD tS3 tS4 tID tID N – 15 N – 14 N – 13 N – 1 N NOTES 1. RECOMMENDED PLACEMENT FOR DATACLK RISING (ACTIVE) EDGE IS NEAR THE SHP OR SHD RISING (ACTIVE) EDGE. THE BEST LOCATION FOR LOWEST NOISE WILL BE SYSTEM DEPENDENT. 2. CCD SIGNAL IS SAMPLED AT SHP AND SHD RISING EDGES. SHP SHD DATACLK OUTPUT DATA CCD SIGNAL (CCDIN) tS1 tCONV tS2 Figure 3. CCD Sampling Timing (Default Polarity Settings) |
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