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NCP348AEMTTBG Datasheet(PDF) 10 Page - ON Semiconductor |
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NCP348AEMTTBG Datasheet(HTML) 10 Page - ON Semiconductor |
10 / 13 page NCP348, NCP348AE http://onsemi.com 10 Undervoltage Lockout (UVLO) To ensure proper operation under any conditions, the device has a built−in undervoltage lockout (UVLO) circuit. During Vin positive going slope, the output remains disconnected from input until Vin voltage is below 3.25 V (NCP348MTT version), plus hysteresis, nominal. The FLAG output is tied to low as long as Vin does not reach UVLO threshold. This circuit has a 50 mV hysteresis to provide noise immunity to transient condition. Additional UVLO thresholds ranging from UVLO can be manufactured. (See Selection Guide on page 12) Contact your ON Semiconductor representative for availability. Overvoltage Lockout (OVLO) To protect connected systems on Vout pin from overvoltage, the device has a built−in overvoltage lockout (OVLO) circuit. During overvoltage condition, the output remains disabled as long as the input voltage exceeds 6.4 V typical (NCP348MTT version). Additional OVLO thresholds ranging from OVLO can be manufactured. (See Selection Guide on page 12) Contact your ON Semiconductor representative for availability. FLAG output is tied to low until Vin is higher than OVLO. This circuit has a 100 mV hysteresis to provide noise immunity to transient conditions. FLAG Output The NCP348 provides a FLAG output, which alerts external systems that a fault has occurred. This pin is tied to low as soon the OVLO threshold is exceeded or when the Vin level is below the UVLO threshold. When Vin level recovers normal condition, FLAG is held high, keeping in mind that an additional 50 ms delay has been added between available output and FLAG = high. The pin is an open drain output, thus a pull up resistor (typically 1 M W, minimum 10 kW) must be added to Vbat. Minimum Vbat supply must be 2.5 V. The FLAG level will always reflects Vin status, even if the device is turned off (EN = 1). EN Input To enable normal operation, the EN pin shall be forced to low or connected to ground. A high level on the pin, disconnects OUT pin from IN pin. EN does not overdrive an OVLO or UVLO fault. Internal NMOS FET The NCP348 includes an internal Low RDS(on) NMOS FET to protect the systems, connected on OUT pin, from positive overvoltage. Regarding electrical characteristics, the RDS(on), during normal operation, will create low losses on Vout pin. As example: Rload = 8.0 W, Vin = 5.0 V Typical RDS(on) = 65 mW, Iout = 618 mA Vout = 8 x 0.618 = 4.95 V NMOS losses = RDS(on) x Iout2 = 0.065 x 0.6182 = 25 mW ESD Tests The NCP348 input pin fully supports the IEC61000−4−2. 1.0 mF (minimum) must be connected between Vin and GND, close to the device. That means, in Air condition, Vin has a "15 kV ESD protected input. In Contact condition, Vin has "8.0 kV ESD protected input. Please refer to Figure 19 to see the IEC 61000−4−2 electrostatic discharge waveform. Figure 19. Electrostatic Discharge Waveform PCB Recommendations The NCP348 integrates a 2 amperes rated NMOS FET, and the PCB rules must be respected to properly evacuate the heat out of the silicon. The PAD1 is internally isolated from the active silicon and should preferably be connected to ground. The PAD2 of the NCP348 package is connected to the internal NMOS drain and can be used to increase the heat transfer if necessary from an applications standpoint. Depending upon the power dissipated in the application, one can either use the PCB tracks connected to Pins 4 and 5 to evacuate heat, or make profit of the PAD2 area to add extra copper surface to reduce the junction temperature (See Figure 20). Of course, in any case, this pad shall be not connected to any other potential. Figure 20 shows copper area according to RqJA and allows the design of the heat transfer plane connected to PAD2. |
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