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CAT706RVI-GT3 Datasheet(PDF) 9 Page - ON Semiconductor |
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CAT706RVI-GT3 Datasheet(HTML) 9 Page - ON Semiconductor |
9 / 12 page CAT705, CAT706, CAT813 http://onsemi.com 9 APPLICATION NOTES mP’s with Bidirectional Reset Pins The RESET output can be pulled low by processors like the 68HC11 allowing for a system reset issued by the processor. The maximum pullup current that can be sourced by the CAT705 & CAT706 1.5 mA (and by the CAT706 T/R/S is 800 mA) allowing the processor to pull the output low even when the CAT70x is pulling it high. Power Transients Generally short duration negative−going transients of less than 2 ms on the power supply at VRST minimum will not cause a reset condition. However the lower the voltage of the transient the shorter the required time to cause a reset output. These issues can usually be remedied by the proper location of bypass capacitance on the circuit board. Output Valid Conditions The RESET output uses a push−pull output which can maintain a valid output down to a VCC of 1.0 volts. To sink current below 0.8 V a resistor can be connected from RESET to Ground (see Figure 11.) This arrangement will maintain a valid value on the RESET output during both power up and down but will draw current when the RESET output is in the high state. A resistor value of about 100 k W should be adequate in most situations to maintain a low condition valid output down to VCC equal to 1.0 V. mC WDI GND PFI CAT705 CAT706 CAT813 100 kW Figure 11. RESET Valid for VCC < 1.0 V RESET/RESET RESET/RESET PFO WDO VCC MR mC I/O LINE INTERRUPT NMI VCC Push Switch 5 V WDI GND PFI CAT705 CAT706 CAT813 UNREGULATED DC Figure 12. Typical Operating Circuit VCC MR PFO WDO RESET/RESET RESET/RESET |
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