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R1EX24002ATAS0G Datasheet(PDF) 9 Page - Renesas Technology Corp

Part # R1EX24002ATAS0G
Description  Two-wire serial interface 2k EEPROM Clock frequency
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R1EX24002ATAS0G Datasheet(HTML) 9 Page - Renesas Technology Corp

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R1EX24002ASAS0G/R1EX24002ATAS0G
Preliminary
Write Operations (WP=Low)
Byte Write: (Write operation during WP=Low status)
A write operation requires an 8-bit device address word with R/W = “0”. Then the EEPROM sends acknowledgment
"0" at the ninth clock cycle. After these, the 2k bit EEPROM receives 8-bit memory address words. Upon receipt of this
memory address, the EEPROM outputs acknowledgment "0" and receives a following 8-bit write data. After receipt of
write data, the EEPROM outputs acknowledgment "0". If the EEPROM receives a stop condition, the EEPROM enters
an internally-timed write cycle and terminates receipt of SCL, SDA inputs until completion of the write cycle. The
EEPROM returns to a standby mode after completion of the write cycle.
Byte Write Operation
Device
address
Memory
address
Write data (n)
2k
10 10
W
Stop
Start
ACK
ACK
R/W
ACK
WP
Page Write:
The EEPROM is capable of the page write operation which allows any number of bytes up to 16 bytes to be written in a
single write cycle. The page write is the same sequence as the byte write except for inputting the more write data. The
page write is initiated by a start condition, device address word, memory address(n) and write data (Dn) with every
ninth bit acknowledgment. The EEPROM enters the page write operation if the EEPROM receives more write data
(Dn+1) instead of receiving a stop condition. The a0 to a3 address bits are automatically incremented upon receiving
write data (Dn+1). The EEPROM can continue to receive write data up to 16 bytes. If the a0 to a3 address bits reaches
the last address of the page, the a0 to a3 address bits will roll over to the first address of the same page and previous
write data will be overwritten. Upon receiving a stop condition, the EEPROM stops receiving write data and enters
internally-timed write cycle.
Page Write Operation
Device
address
Memory
address (n)
Write data (n+m)
Write data (n)
2k
10 10
W
Stop
Start
ACK
ACK
ACK
ACK
R/W
WP
R10DS0078EJ0100 Rev.1.00
Page 9 of 16
Mar. 06, 2013


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