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R1EX24004ASAS0G Datasheet(PDF) 6 Page - Renesas Technology Corp

Part # R1EX24004ASAS0G
Description  Two-wire serial interface 4k EEPROM Clock frequency
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

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R1EX24004ASAS0G/R1EX24004ATAS0G
Preliminary
Pin Function
Serial Clock (SCL)
The SCL pin is used to control serial input/output data timing. The SCL input is used to positive edge clock data into
EEPROM device and negative edge clock data out of each device. Maximum clock rate is 400 kHz.
Serial Input/Output Data (SDA)
The SDA pin is bidirectional for serial data transfer. The SDA pin needs to be pulled up by resistor as that pin is open-
drain driven structure. Use proper resistor value for your system by considering VOL, IOL and the SDA pin capacitance.
Except for a start condition and a stop condition which will be discussed later, the SDA transition needs to be completed
during the SCL low period.
Data Validity (SDA data change timing waveform)
SCL
SDA
Data
change
Data
change
Note:
High-to-low and low-to-high change of SDA should be done during the SCL low period.
Device Address (A0, A1, A2)
Four devices can be wired for one common data bus line as maximum. Device address pins are used to distinguish each
device and device address pins should be connected to VCC or VSS. When device address code provided from SDA pin
matches corresponding hard-wired device address pins A0 to A2, that one device can be activated.
Pin Connections for A0 to A2
Pin connection
Memory size
Max connect
number
A2
A1
A0
Note
4k bit
4
VCC/VSS *
1
VCC/VSS *
1
 *2
Use A0 for memory address a8
Note: 1. During floating, “VCC/VSS” are fixed to VSS , because these are internally pulled-down.
2. Floating state can be possible, because it is not connected inside.
Write Protect (WP)
When the Write Protect pin (WP) is high, the write protection feature is enabled and operates as shown in the following
table. Also, acknowledgment "0" is outputted after inputting device address and memory address. After inputting write
data, acknowledgment "1"(NO ACK) is outputted.
When the WP is low, write operation for all memory arrays are allowed. The read operation is always activated
irrespective of the WP pin status.
The WP pin is internally pulled-down to VSS. Write operations for all memory array are allowed if unconnected.
Write Protect Area
Write protect area
WP pin status
4k bit
VIH
Full (4k bit)
VIL
Normal read/write operation
R10DS0079EJ0100 Rev.1.00
Page 6 of 16
Mar. 06, 2013


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