7

FN6381.0

October 12, 2006

Applications Usage

Using the ISL870XAEVAL1 Platform

The ISL870XAEVAL1 platform is the primary evaluation

board for this family of sequencers. See Figure 16 for

photograph and schematic.The evaluation board is shipped

with an ISL8702A mounted in the left position and with the

other device variants loose packed. In the following

discussion, test points names are bold on initial occurrence

for identification.

3.3V to 24V. The VHI test point is for the ENABLE and

FAULT pull-up voltage which are limited to a maximum of

that a nominal 12V on the VMONITOR test point is compliant

and with a rising OV set at 13.2V and a falling UV set at

are brought out separately for maximum flexibility in

evaluation.

VMONITOR ramping up and down through the UV and OV

levels will result in the FAULT output signaling the out of

bound conditions by being released to pull high to the VHI

voltage as shown in Figures 6 and 7.

Once the voltage monitoring FAULT is resolved and where

applicable, the SEQ_EN(#) is satisfied, sequencing of the

ENABLE_X(#) outputs begins. When sequence enabled the

ENABLE_A, ENABLE_B, ENABLE_C and lastly

ENABLE_D are asserted in that order and when SEQ_EN is

disabled the order is reversed. See Figures 8 and 9

demonstrating the sequenced enabling and disabling of the

ENABLE outputs. The timing between ENABLE outputs is

set by the resistor values on the TB, TC, TD pins as shown.

Figure 10 illustrates the timing from either SEQ_EN and/or

VMONITOR being valid to ENABLE_A being asserted with a

10nF TIME capacitor. Figure 11 shows that ENABLE_X

to ensure that a false enable is not signaled. Figure 12

illustrates the SEQ_EN# input disabling and enabling the

ISL8705A ENABLE# outputs. Notice the reversal in order

and delay timing from ENABLE_X# to ENABLE_X#.

Figure 13 shows the time from SEQ_EN transition with the

voltage ramping across the TIME capacitor to TIME Vth

being met. This results in the immediate pull down of the

TIME pin and simultaneous ENABLE_A enabling.

FIGURE 3. ISL8702A, ISL8703A, ISL8704A, ISL8705A FAULT OPERATIONAL DIAGRAM

UNDERVOLTAGE

OVERVOLTAGE

MONITORED VOLTAGE

FAULT OUTPUT

LIMIT

LIMIT

RAMPING UP AND DOWN

Typical Performance Curves

FIGURE 4. UV/OV RISING THRESHOLD

1.198

1.199

1.200

1.201

1.202

1.203

1.204

1.205

1.206

1.207

1.208

-40

-10

0

25

60

85

100

TEMP (°C)

150

170

190

210

230

250

270

290

310

-40

-10

0

25

60

85

100

TEMP (°C)

ISL8700A, ISL8701A, ISL8702A, ISL8703A, ISL8704A, ISL8705A