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R1EX24016ASAS0G Datasheet(PDF) 4 Page - Renesas Technology Corp |
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R1EX24016ASAS0G Datasheet(HTML) 4 Page - Renesas Technology Corp |
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4 / 18 page  R1EX24016ASAS0G/R1EX24016ATAS0G R10DS0032EJ0200 Rev.2.00 Page 4 of 16 Feb. 13, 2013 AC Characteristics Test Conditions Input pules levels: VIL = 0.2 VCC VIH = 0.8 VCC Input rise and fall time: 20 ns Input and output timing reference levels: 0.5 VCC Output load: TTL Gate + 100 pF (Ta = 40 to +105C, VCC = 1.8 to 5.5 V) Parameter Symbol Min Typ Max Unit Notes Clock frequency fSCL 400 kHz Clock pulse width low tLOW 1200 ns Clock pulse width high tHIGH 600 ns Noise suppression time tI 50 ns 1 Access time tAA 100 900 ns Bus free time for next mode tBUF 1200 ns Start hold time tHD.STA 600 ns Start setup time tSU.STA 600 ns Data in hold time tHD.DAT 0 ns Data in setup time tSU.DAT 100 ns Input rise time tR 300 ns 1 Input fall time tF 300 ns 1 Stop setup time tSU.STO 600 ns Data out hold time tDH 50 ns Write protect hold time tHD.WP 1200 ns Write protect setup time tSU.WP 0 ns Write cycle time tWC 5 ms 2 Notes: 1. Not 100 tested. 2. tWC is the time from a stop condition to the end of internally controlled write cycle. |
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