Datasheet

R2A20169NP/SA/SP

Page 5 of 9

R03DS0020EJ0300 Rev.3.00

Jul 25, 2013

Item

Symbol

Test conditions

Limits

Unit

Min

Typ

Max

Clock frequency

-

1.0

10

MHz

Clock low pulse width

40

-

-

ns

Clock high pulse width

40

-

-

ns

Clock rise time

-

-

200

ns

Clock fall time

-

-

200

ns

Data setup time

4

-

-

ns

Data hold time

30

-

-

ns

LD setup time

40

-

-

ns

LD hold time

40

-

-

ns

LD high pulse width

40

-

-

ns

Data output delay time

-10

-

50

ns

D/A output settling time

¨4.5V,

The time until the output becomes the final

value of 1/2 LSB.

-

-

150

µs

AC Characteristics

Timing Chart

CLK

DI

LD

D/A

output

Do

output

(Note) Timing chart above is a schematic representation of the timing of each signal type.

CLK signal input is High or Low regardless, LD signal High input is enabled.