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PD46364092BF1-E40-EQ1-A Datasheet(PDF) 6 Page - Renesas Technology Corp |
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PD46364092BF1-E40-EQ1-A Datasheet(HTML) 6 Page - Renesas Technology Corp |
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6 / 36 page  μPD46364092B, μPD46364182B, μPD46364362B R10DS0091EJ0400 Rev.4.00 Page 6 of 35 Nov 09, 2012 Pin Description (1/2) Symbol Type Description A0 A Input Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of K. All transactions operate on a burst of two words (one clock period of bus activity). A0 is used as the lowest order address bit permitting a random starting address within the burst operation on x18 and x36 devices. These inputs are ignored when device is deselected, i.e., NOP (LD# = HIGH). DQ0 to DQxx Input/Outpu t Synchronous Data IOs: Input data must meet setup and hold times around the rising edges of K and K#. Output data is synchronized to the respective C and C# data clocks or to K and K# if C and C# are tied to HIGH. x9 device uses DQ0 to DQ8. x18 device uses DQ0 to DQ17. x36 device uses DQ0 to DQ35. LD# Input Synchronous Load: This input is brought LOW when a bus cycle sequence is to be defined. This definition includes address and read/write direction. All transactions operate on a burst of 2 data (one clock period of bus activity). R, W# Input Synchronous Read/Write Input: When LD# is LOW, this input designates the access type (READ when R, W# is HIGH, WRITE when R, W# is LOW) for the loaded address. R, W# must meet the setup and hold times around the rising edge of K. BWx# Input Synchronous Byte Writes: When LOW these inputs cause their respective byte to be registered and written during WRITE cycles. These signals must meet setup and hold times around the rising edges of K and K# for each of the two rising edges comprising the WRITE cycle. See Pin Arrangement for signal to data relationships. x9 device uses BW0#. x18 device uses BW0#, BW1#. x36 device uses BW0# to BW3#. See Byte Write Operation for relation between BWx# and Dxx. K, K# Input Input Clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data on the rising edge of K and the rising edge of K#. K# is ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges. C, C# Input Output Clock: This clock pair provides a user controlled means of tuning device output data. The rising edge of C# is used as the output timing reference for first output data. The rising edge of C is used as the output reference for second output data. Ideally, C# is 180 degrees out of phase with C. When use of K and K# as the reference instead of C and C#, then fixed C and C# to HIGH. Operation cannot be guaranteed unless C and C# are fixed to HIGH (i.e. toggle of C and C#) |
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