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A918CY-4R7M Datasheet(PDF) 10 Page - Analog Devices |
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A918CY-4R7M Datasheet(HTML) 10 Page - Analog Devices |
10 / 22 page REV. –10– ADN8830 To eliminate the resolution of the DAC as the principal source of system error, the step size of each bit, VSTEP, should be lower than the desired system resolution. A practical value for absolute DAC resolution is the equivalent of 0.05 °C. The value of VSTEP should be less than the value of m from Equation 8 multiplied by the desired temperature resolution, or VC m STEP <° × 005 . (10) where m is the slope of the voltage-to-temperature conversion line, as found from Equation 8. From Design Example 2, where m = 25 mV/ °C, we see the DAC should have resolution better than 1.25 mV per step. The minimum number of bits required is then given as Number of Bits VV FS STEP = () ( ) () log – log log 2 (11) where VFS is the full-scale output voltage from the DAC, which should be equal to the reference voltage from the ADN8830, VREF = 2.47 V as given in the Specifications table for the Reference Voltage. In this example, the minimum resolution is 11 bits. A 12-bit DAC, such as the AD7390, can be readily found. It is important that the full-scale voltage input to the DAC is tied to the ADN8830 reference voltage, as shown in Figure 4. This eliminates errors from slight variances of VREF. Thermistor Fault and Temperature Lock Indications Both the THERMFAULT (Pin 1) and TEMPLOCK (Pin 5) outputs are CMOS compatible outputs that are active high. THERMFAULT will be a logic low while the thermistor is operating normally and will go to a logic high if a short or open is detected at THERMIN (Pin 2). The trip voltage for THERMFAULT is when THERMIN falls below 0.2 V or exceeds 2.0 V. THERMFAULT provides only an indication of a fault condition and does not activate any shutdown or protec- tion circuitry on the ADN8830. To shut down the ADN8830, a logic low voltage must be asserted on Pin 3, as described in the Shutdown Mode section. TEMPLOCK will output a logic high when the voltage at THERMIN is within 2.5 mV of TEMPSET. This voltage can be related to temperature by solving for m from Equation 8. For most laser diode applications, 2.5 mV is equivalent to ±0.1°C. If the voltage difference between THERMIN and TEMPSET is greater than 2.5 mV, then TEMPLOCK will output a logic low. The input offset voltage of the ADN8830 is guaranteed to within 250 μV, which for most applications is within ±0.01°C. Setting the Switching Frequency The ADN8830 has an internal oscillator to generate the switch- ing frequency for the output stage. This oscillator can be either set in free-run mode or synchronized to an external clock signal. For free-run operation, SYNCIN (Pin 25) should be connected to ground and COMPOSC (Pin 24) should be connected to AVDD. The switching frequency is then set by a single resistor connected from FREQ (Pin 26) to ground. Table I shows RFREQ for some common switching frequencies. Table I. Switching Frequencies vs. RFREQ fSWITCH RFREQ 100 kHz 1.5 M Ω 250 kHz 600 k Ω 500 kHz 300 k Ω 750 kHz 200 k Ω 1 MHz 150 k Ω For other frequencies, the value for this resistor, RFREQ, should be set to R f FREQ SWITCH = × 150 10 9 (12) where fSWITCH is the switching frequency in Hz. Higher switching frequencies reduce the voltage ripple across the TEC. However, high switch frequencies will create more power dissipation in the external transistors. This is due to the more frequent charging and discharging of the transistors’ gate capacitances. If large transistors are needed for a high output current application, faster switching frequencies could reduce the overall power efficiency of the circuit. This is covered in detail in the Calculating Power Dissipation and Efficiency section. The switching frequency of the ADN8830 can be synchronized with an external clock by connecting the clock signal to SYNCIN (Pin 25). Pin 24 should also be connected to an R-C network, as shown in Figure 6. This network is simply used to compensate a PLL to lock on to the external clock. To ensure the quickest synchronization lock-in time, RFREQ should be set to 1.5 M Ω. ADN8830 FREQ COMPOSC 1.5M 26 24 0.1 F 1k 1nF Figure 6. Using an R-C Network on Pin 24 with an External Clock The relative phase of the ADN8830 internal oscillator compared to the external clock signal can be adjusted. This is accomplished by adjusting the voltage to PHASE (Pin 29) according to TPCs 3 and 4. The phase shift versus voltage can be approximated as Phase Shift V VREF PHASE °= ° × 360 (13) where VPHASE is the voltage at Pin 29, and VREF has a typical value of 2.47 V. To ensure the oscillator operates correctly, VPHASE should remain higher than 100 mV and lower than 2.3 V. This is required for either internal clock or external synchronization operation. A resistor divider from VREF to ground can establish this voltage easily, although any voltage source, such as a DAC, could be used as well. If phase is not a consideration, for example with a single ADN8830 being used, Pin 29 can be tied to Pin 6, which pro- vides a 1.5 V reference voltage. D |
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