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R1QBA4436RBG Datasheet(PDF) 9 Page - Renesas Technology Corp |
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R1QBA4436RBG Datasheet(HTML) 9 Page - Renesas Technology Corp |
9 / 37 page PAGE : ‹#› Rev. 0.11b : 2012.06.05 R1QBA44**RBG / R1QEA44**RBG Series (Preliminary) hinS=00000.0000.0000.0000.0000--- 00000.0000.0000.0000.0000---11111.1111.1111.1111.1111--- 144M Status Power Up & Unstable Stage NOP & Set-up Stage Normal Operation V DD SET-UP Cycle V DDQ V REF /DOFF 2. Double clock mode K, /K Fix High (=Vddq) C, /C Status Power Up & Unstable Stage NOP & Set-up Stage Normal Operation V DD SET-UP Cycle V DDQ V REF /DOFF 1. Single clock mode (C and /C pins fixed High) K, /K Fix High (=Vddq) General Description Power-up and Initialization Sequence -V DD must be stable before K, /K clocks are applied. - Recommended voltage application sequence : V SS V DD V DDQ & VREF V IN. (0 V to VDD, VDDQ < 200 ms) - Apply V REF after VDDQ or at the same time as VDDQ. - Then execute either one of the following three sequences. 1. Single Clock Mode (C and /C tied high) - Drive /DOFF high (/DOFF can be tied high from the start). - Then provide stable clocks (K, /K) for at least 20 us. 2. Double Clock Mode (C and /C control outputs) (II series only) - Drive /DOFF high (/DOFF can be tied high from the start) - Then provide stable clocks (K, /K , C, /C) for at least 20 us. 3. DLL/PLL Off Mode (/DOFF tied low) - In the "NOP and setup stage", provide stable clocks (K, /K) for at least 20 us. R10DS0189EJ0011 |
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