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DLP4500 Datasheet(PDF) 9 Page - Texas Instruments |
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DLP4500 Datasheet(HTML) 9 Page - Texas Instruments |
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9 / 36 page  DLP4500 www.ti.com DLPS028A – APRIL 2013 – REVISED MAY 2013 Table 3. Connector Pins for FQE TERMINAL CONNECTOR INTERNAL CLOCKED DATA I/O/P TYPE DESCRIPTION NAME PINS TERMINATION BY RATE Data Inputs DATA(0) C12 Input LVCMOS None DCLK DDR DATA(1) C10 Input LVCMOS None DCLK DDR DATA(2) C9 Input LVCMOS None DCLK DDR DATA(3) C7 Input LVCMOS None DCLK DDR DATA(4) C4 Input LVCMOS None DCLK DDR DATA(5) C6 Input LVCMOS None DCLK DDR DATA(6) C3 Input LVCMOS None DCLK DDR DATA(7) C13 Input LVCMOS None DCLK DDR DATA(8) C15 Input LVCMOS None DCLK DDR DATA(9) C16 Input LVCMOS None DCLK DDR DATA(10) C18 Input LVCMOS None DCLK DDR DATA(11) C19 Input LVCMOS None DCLK DDR Input data bus DATA(12) C21 Input LVCMOS None DCLK DDR DATA(13) C22 Input LVCMOS None DCLK DDR DATA(14) D22 Input LVCMOS None DCLK DDR DATA(15) D21 Input LVCMOS None DCLK DDR DATA(16) D19 Input LVCMOS None DCLK DDR DATA(17) D4 Input LVCMOS None DCLK DDR DATA(18) D9 Input LVCMOS None DCLK DDR DATA(19) D10 Input LVCMOS None DCLK DDR DATA(20) D6 Input LVCMOS None DCLK DDR DATA(21) D16 Input LVCMOS None DCLK DDR DATA(22) D7 Input LVCMOS None DCLK DDR DATA(23) D15 Input LVCMOS None DCLK DDR DCLK D13 Input LVCMOS None – – Input data bus clock Data Control Inputs LOADB D12 Input LVCMOS None DCLK DDR Parallel data load enable TRC D3 Input LVCMOS None DCLK DDR Input data toggle rate control SCTRL D18 Input LVCMOS None DCLK DDR Serial control bus Stepped address control serial bus SAC_BUS D33 Input LVCMOS None SAC_CLK – data Stepped address control serial bus SAC_CLK D29 Input LVCMOS None – – clock Mirror Reset Control Inputs DRC_BUS C29 Input LVCMOS None SAC_CLK DMD reset-control serial bus Active-low output enable signal for DRC_OE C33 Input LVCMOS None – – internal DMD Reset driver circuitry Strobe signal for DMD Reset DRC_STROBE C36 Input LVCMOS None SAC_CLK Control inputs Power VBIAS C31, C32 Power Analog None – – Mirror Reset Bias Voltage VOFFSET D25, D26 Power Analog None – – Mirror Reset Offset Voltage VRESET D31, D32 Power Analog None – – Mirror Reset Voltage Power Supply for Low Voltage VREF C25, C26 Power Analog None – – CMOS Double-Data-Rate (DDR) Interface Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: DLP4500 |
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