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MCIMX6X7DYM08AC Datasheet(PDF) 6 Page - Freescale Semiconductor, Inc |
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MCIMX6X7DYM08AC Datasheet(HTML) 6 Page - Freescale Semiconductor, Inc |
6 / 165 page i.MX 6Dual/6Quad Automotive and Infotainment Applications Processors, Rev. 2.3 6 Freescale Semiconductor Introduction – 1-bit, 4-bit, or 8-bit transfer mode specifications for MMC cards up to 52 MHz in both SDR and DDR modes (104 MB/s max) •USB: — One High Speed (HS) USB 2.0 OTG (Up to 480 Mbps), with integrated HS USB PHY — Three USB 2.0 (480 Mbps) hosts: – One HS host with integrated High Speed PHY – Two HS hosts with integrated HS-IC USB (High Speed Inter-Chip USB) PHY • Expansion PCI Express port (PCIe) v2.0 one lane — PCI Express (Gen 2.0) dual mode complex, supporting Root complex operations and Endpoint operations. Uses x1 PHY configuration. • Miscellaneous IPs and interfaces: — Three I2S/SSI/AC97, up to 1.4 Mbps each — Enhanced Serial Audio Interface (ESAI), up to 1.4 Mbps per channel — Five UARTs, up to 4.0 Mbps each: – Providing RS232 interface – Supporting 9-bit RS485 multidrop mode – One of the five UARTs (UART1) supports 8-wire while others four supports 4-wire. This is due to the SoC IOMUX limitation, since all UART IPs are identical. — Five eCSPI (Enhanced CSPI) — Three I2C, supporting 400 kbps — Gigabit Ethernet Controller (IEEE1588 compliant), 10/100/10001 Mbps — Four Pulse Width Modulators (PWM) — System JTAG Controller (SJC) — GPIO with interrupt capabilities — 8x8 Key Pad Port (KPP) — Sony Philips Digital Interconnect Format (SPDIF), Rx and Tx — Two Controller Area Network (FlexCAN), 1 Mbps each — Two Watchdog timers (WDOG) — Audio MUX (AUDMUX) — MLB (MediaLB) provides interface to MOST Networks (150 Mbps) with the option of DTCP cipher accelerator The i.MX 6Dual/6Quad processors integrate advanced power management unit and controllers: • Provide PMU, including LDO supplies, for on-chip resources • Use Temperature Sensor for monitoring the die temperature • Support DVFS techniques for low power modes • Use Software State Retention and Power Gating for ARM and MPE 1. The theoretical maximum performance of 1 Gbps ENET is limited to 470 Mbps (total for Tx and Rx) due to internal bus throughput limitations. The actual measured performance in optimized environment is up to 400 Mbps. For details, see the ERR004512 erratum in the i.MX 6Dual/6Quad errata document (IMX6DQCE). |
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