ICS874001AGI-05 REVISION A JANUARY 14, 2011

2

©2011 Integrated Device Technology, Inc.

ICS74001I-05 Data Sheet

PCI EXPRESS™ JITTER ATTENUATOR

Table 1. Pin Descriptions

NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.

Table 2. Pin Characteristics

Number

Name

Type

Description

1

PLL_SEL

Input

Pullup

PLL select pin. When LOW, bypasses the PLL. When HIGH selects the PLL.

LVCMOS/LVTTL interface levels. See Table 3B.

2, 3, 4, 6,

15, 16, 20

nc

Unused

No connect.

5

MR

Input

Pulldown

Active High Master Reset. When logic HIGH, the internal dividers are reset

causing the true output Q to go LOW and the inverted output nQ to go HIGH.

When logic LOW, the internal dividers and the outputs are enabled.

LVCMOS/LVTTL interface levels.

7

F_SEL1

Input

Pullup

Frequency select pin. LVCMOS/LVTTL interface levels. See Table 3C.

Power

Analog supply pin.

9

F_SEL0

Input

Pulldown

Frequency select pin. LVCMOS/LVTTL interface levels. See Table 3C.

10

Power

Core supply pin.

11

OE

Input

Pullup

Output enable. When HIGH, outputs are enabled. When LOW, forces outputs

to a High-Impedance state. LVCMOS/LVTTL interface levels. See Table 3A.

12

CLK

Input

Pulldown

Non-inverting differential clock input.

13

nCLK

Input

Pullup

Inverting differential clock input.

14

GND

Power

Power supply ground.

17, 18

nQ, Q

Output

Differential output pair. LVDS interface levels.

19

Power

Output supply pin.

Symbol

Parameter

Test Conditions

Minimum

Typical

Maximum

Units

Input Capacitance

4pF

Input Pullup Resistor

51

k

Ω

Input Pulldown Resistor

51

k

Ω