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HI-6121 Datasheet(PDF) 1 Page - Holt Integrated Circuits |
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HI-6121 Datasheet(HTML) 1 Page - Holt Integrated Circuits |
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1 / 158 page  HOLT INTEGRATED CIRCUITS www.holtic.com 1 June, 2012 HI-6120 Parallel Bus Interface and HI-6121 Serial Peripheral Interface (SPI) MIL-STD-1553 Remote Terminal ICs DS6120 Rev. C 06/12 FEATURES • Fully integrated 3.3V Remote Terminal meets all requirements for MIL-STD-1553B Notice 2 • Four data buffer modes for subaddress transmit and receive commands. Data buffer modes are independently selectable for transmit and receive commands on each subaddress • Simplifiedmodecodecommandhandling • Integral 16-bit Time-Tag counter has programma- ble options for clock, interrupts and auto-synchro- nization • Message information and time-tag words are stored with message data words for all transacted messages • In compliance with MIL-STD-1553B Notice 2, re- ceived data from broadcast messages may be optionally separated from non-broadcast received data • Optional interrupt log buffer stores the most recent 16 interrupts to minimize host service duties • Optional illegal command detection uses internal table • Optional automatic self-initialization at reset • ±8kV ESD Protection (HBM, all pins) • MIL-STD-1760 compliant PIN CONFIGURATION (TOP) GENERAL DESCRIPTION The HI-6120 and HI-6121 provide a complete, integrated, 3.3V MIL-STD-1553 Remote Terminal in a monolithic sili- con gate CMOS device. Two host interface options are offered: The HI-6120 uses a 16-bit parallel host bus inter- face for access to registers and RAM and is offered in a 100-pinplasticquadflatpack(PQFP).TheHI-6121has a 4-wire SPI (Serial Peripheral Interface) host connection andcomesinareducedpincount52-pinPQFPor9mm x9mm64-pinQFN.Bothdeviceshandleallaspectsof the MIL-STD-1553 protocol, including message encod- ing, decoding, error detection, illegal command detection anddatabuffering.Hostdatamanagementissimplified by storing message information and data within the on- chip 32K x 16 static RAM. A descriptor table in shared RAM provides fully program- mable memory management. Multiple descriptor tables can be implemented for fast context switching. Trans- mit and receive commands can use any of four differ- ent data buffer modes: indexed (single) buffering, ping- pong (double) buffering or two circular buffer schemes. Transmit and receive commands for each subaddress may use different buffer modes. Mode code commands employ a simple scheme for storing mode data and mes- sage information with programmable interrupts. The device provides internal illegalization capability, allowing any subset of subaddress, command T/R bit, broadcast vs non-broadcast and word count (or mode code)tobeillegalized,resultinginatotalof4,096pos- sible combinations. The illegalization table resides in in- ternal RAM. The RT can also operate without illegal com- mand detection, providing “in form” responses to all valid commands. Broadcast command recognition is optional. The HI-6120 and HI-6121 provide programmable inter- rupts for automatic message handling, message status and general status. A host interrupt history log maintains information about the last 16 interrupts. TheHI-6120andHI-6121canbeconfiguredforautomat- ic self-initialization. A dedicated SPI port reads data from externalserialEEPROMmemorytofullyconfigurethe descriptor table, illegalization table and host interrupts. Internal dual-redundant transceivers provide direct connection to bus isolation transformers. The device is offered with industrial temperature range as well as extended temperature range with optional burn-in. A “RoHS compliant” lead-free option is also offered. HI-6121 in PQFP-52 Package 39 - TEST 38 -LOCK 37 -MTSTOFF 36 - BUSA 35 - VCCP 34 - 33 - 32 - VCCP 31 - 30 - 29 - 28 - 27 - TEST3 BUSA BUSB BUSB TEST0 TEST1 TEST2 COMP -1 -2 MODE- 3 SI -4 SCK -5 SO -6 MCLK -7 RTA0 -8 RTA1 -9 RTA2 -10 -11 RTA3 -12 RTA4 -13 CE MR HI-6121PQx |
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