LMH0344

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SNLS233L – APRIL 2007 – REVISED APRIL 2013

DEVICE OPERATION

BLOCK DESCRIPTION

The Equalizer Filter block is a multi-stage adaptive filter. If Bypass is high, the equalizer filter is disabled.

The DC Restoration / Level Control block receives the differential signals from the equalizer filter block. This

block incorporates a self-biasing DC restoration circuit to fully DC restore the signals. If Bypass is high, this

function is disabled.

The signals before and after the DC Restoration / Level Control block are used to generate the Automatic

Equalization Control (AEC) signal. This control signal sets the gain and bandwidth of the equalizer filter. The

loop response in the AEC block is controlled by an external 1µF capacitor placed across the AEC+ and AEC-

pins.

The Carrier Detect / Mute block generates the carrier detect signal and controls the mute function of the output.

The Output Driver produces SDO and SDO.

The mute reference sets the threshold for CD and (with CD tied to MUTE) determines the amount of cable to

equalize before automatically muting the outputs. This is set by applying a voltage inversely proportional to the

may be left unconnected or connected to ground for maximum equalization before muting.

CARRIER DETECT (CD) AND MUTE

detect threshold will be altered accordingly. CD provides a high voltage when no signal is present at the

LMH0344 input. CD is low when a valid input signal is detected.

MUTE can be used to manually mute or enable SDO and SDO. Applying a high input to MUTE will mute the

LMH0344 outputs by forcing the output to a logic zero. Applying a low input will force the outputs to be active.

CD and MUTE may be tied together to automatically mute the output when no input signal is present.

INPUT INTERFACING

The LMH0344 accepts either differential or single-ended input. The input must be AC coupled. Transformer

coupling is not supported.

The LMH0344 correctly handles equalizer pathological signals for standard definition and high definition serial

digital video, as described in SMPTE RP 178 and RP 198, respectively.

OUTPUT INTERFACING

The SDO and SDO outputs are internally loaded with 50

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