ADG1204YCPZ-500RL7 datasheet(8/16 Pages) AD

Part #	ADG1204YCPZ-500RL7

Description	Low Capacitance, Low Charge Injection, 짹15 V/12 V, 4:1 iCMOS Multiplexer

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ADG1204

Rev. B | Page 8 of 16

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS

TOP VIEW

(Not to Scale)

1

2

3

4

5

EN

6

7

NC = NO CONNECT

VSS

S1

S2

A0

NC

D

14

13

12

11

10

GND

VDD

S3

S4

A1

ADG1204

PIN 1

INDICATOR

NC = NO CONNECT

1

VSS

2

S1

3

S2

9GND

8VDD

7S3

TOP VIEW

(Not to Scale)

ADG1204

NOTES

9

8

NC

Figure 2. TSSOP Pin Configuration

1. EXPOSED PAD TIED TO SUBSTRATE, VSS.

Figure 3. LFCSP_VQ Pin Configuration

Table 4. Pin Function Descriptions

Pin No.

Mnemonic

Description

TSSOP

LFCSP_VQ

1

11

A0

Logic Control Input.

2

12

EN

Active High Digital Input. When low, the device is disabled and all switches are off.

When high, Ax logic inputs determine on switches.

3

1

VSS

Most Negative Power Supply Potential.

4

2

S1

Source Terminal. Can be an input or an output.

5

3

S2

Source Terminal. Can be an input or an output.

6

4

D

Drain Terminal. Can be an input or an output.

7 to 9

5

NC

No Connection.

10

6

S4

Source Terminal. Can be an input or an output.

11

7

S3

Source Terminal. Can be an input or an output.

12

8

VDD

Most Positive Power Supply Potential.

13

9

GND

Ground (0 V) Reference.

14

10

A1

Logic Control Input.

TRUTH TABLE

Table 5.

EN

A1

A0

S1

S2

S3

S4

0

X

Off

1

0

On

Off

1

0

1

Off

On

Off

1

0

Off

On

Off

1

Off

On

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