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5AGXFA1D627I4N Datasheet(PDF) 11 Page - Altera Corporation |
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5AGXFA1D627I4N Datasheet(HTML) 11 Page - Altera Corporation |
11 / 82 page Chapter 1: Overview for the Arria V Device Family 1–5 Arria V Family Plan February 2012 Altera Corporation Arria V Device Handbook Volume 1: Device Overview and Datasheet Table 1–3. Maximum Resource Counts for Arria V GT, SX, and ST Devices—Preliminary Feature Arria V GT Device Arria V SX Device Arria V ST Device 5AGTD3 5AGTD7 5ASXB3 5ASXB5 5ASTD3 5ASTD5 ALMs 136,880 190,240 132,075 174,340 132,075 174,340 LE (K) 362 504 350 462 350 462 M10K memory blocks 1,726 2,414 1,729 2,282 1,729 2,282 MLAB memory (Kb) 2,098 2,906 2,014 2,658 2,014 2,658 Block memory (Kb) 17,260 24,140 17,288 22,820 17,288 22,820 Variable-precision DSP blocks 1,045 1,156 809 1,068 809 1,068 18 x 19 multipliers 2,090 2,312 1,618 2,186 1,618 2,186 FPGA Fractional PLLs (1) 12 16 TBD TBD TBD TBD HPS PLLs (1) — — TBD TBD TBD TBD FPGA GPIO 704 704 528 528 528 528 HPS I/O — — 216 216 216 216 LVDS TX (2) 160 160 120 120 120 120 LVDS RX (2) 176 176 120 120 120 120 PCIe hard IP blocks 222222 Hard memory controllers 443333 HPS memory controllers — — 1111 ARM Cortex–A9 MPCore processor — — Dual-core Dual-core Dual-core Dual-core Notes to Table 1–3: (1) The total number of available fractional PLLs is a combination of general-purpose and transceiver PLLs. Transceiver fractional PLLs, when not used by the transceiver I/O, can be used as a general-purpose fractional PLL. (2) For the LVDS channels count for each package, refer to the High-Speed Differential I/O Interfaces with DPA in Arria V Devices chapter. |
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