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5AGXFA3D627C3ES Datasheet(PDF) 10 Page - Altera Corporation |
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5AGXFA3D627C3ES Datasheet(HTML) 10 Page - Altera Corporation |
10 / 37 page Maximum Resources Table 8: Maximum Resource Counts for Arria V GZ Devices—Preliminary Member Code Resource E7 E5 E3 E1 450 400 360 220 Logic Elements (LE) (K) 169,800 150,960 135,840 83,020 ALM 679,200 603,840 543,360 332,080 Register 34,000 28,800 19,140 11,700 M20K Memory (Kb) 5,306 4,718 4,245 2,594 MLAB 1,139 1,092 1,044 800 Variable-precision DSP Block 2,278 2,184 2,088 1,600 18 x 18 Multiplier 24 24 20 20 PLL 9 36 36 24 24 12.5 Gbps Transceiver 674 674 414 414 GPIO 10 166 166 99 99 Transmitter LVDS 11 168 168 108 108 Receiver 1 1 1 1 PCIe Hard IP Block Related Information High-Speed Differential I/O Interfaces and DPA in Arria V Devices chapter, Arria V Device Handbook Provides the number of LVDS channels in each device package. Package Plan Table 9: Package Plan for Arria V GZ Devices—Preliminary F1517 (40 mm) F1152 (35 mm) H780 (29 mm) Member Code XCVR GPIO XCVR GPIO XCVR GPIO — — 24 414 12 342 E1 — — 24 414 12 342 E3 36 674 24 534 — — E5 36 674 24 534 — — E7 9 The number of PLLs includes general-purpose fractional PLLs and transceiver fractional PLLs. 10 The number of GPIOs does not include transceiver I/Os. In the Quartus II software, the number of user I/Os includes transceiver I/Os. 11 Arria V Device Overview Altera Corporation Feedback AV-51001 Maximum Resources 10 2013.05.06 |
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