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EP2S5F1508C5ES Datasheet(PDF) 11 Page - Altera Corporation

Part # EP2S5F1508C5ES
Description  Stratix II Device Family Data Sheet
Download  238 Pages
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Manufacturer  ALTERA [Altera Corporation]
Direct Link  http://www.altera.com
Logo ALTERA - Altera Corporation

EP2S5F1508C5ES Datasheet(HTML) 11 Page - Altera Corporation

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Altera Corporation
2–3
May 2007
Stratix II Device Handbook, Volume 1
Stratix II Architecture
The number of M512 RAM, M4K RAM, and DSP blocks varies by device
along with row and column numbers and M-RAM blocks. Table 2–1 lists
the resources available in Stratix II devices.
Logic Array
Blocks
Each LAB consists of eight ALMs, carry chains, shared arithmetic chains,
LAB control signals, local interconnect, and register chain connection
lines. The local interconnect transfers signals between ALMs in the same
LAB. Register chain connections transfer the output of an ALM register to
the adjacent ALM register in an LAB. The Quartus® II Compiler places
associated logic in an LAB or adjacent LABs, allowing the use of local,
shared arithmetic chain, and register chain connections for performance
and area efficiency. Figure 2–2 shows the Stratix II LAB structure.
Table 2–1. Stratix II Device Resources
Device
M512 RAM
Columns/Blocks
M4K RAM
Columns/Blocks
M-RAM
Blocks
DSP Block
Columns/Blocks
LAB
Columns
LAB Rows
EP2S15
4 / 104
3 / 78
0
2 / 12
30
26
EP2S30
6 / 202
4 / 144
1
2 / 16
49
36
EP2S60
7 / 329
5 / 255
2
3 / 36
62
51
EP2S90
8 / 488
6 / 408
4
3 / 48
71
68
EP2S130
9 / 699
7 / 609
6
3 / 63
81
87
EP2S180
11 / 930
8 / 768
9
4 / 96
100
96


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