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5AGXMA3D627I4N Datasheet(PDF) 8 Page - Altera Corporation |
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5AGXMA3D627I4N Datasheet(HTML) 8 Page - Altera Corporation |
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8 / 37 page  Maximum Resources Table 6: Maximum Resource Counts for Arria V GT Devices—Preliminary Member Code Resource D7 D3 C7 C3 504 362 242 156 Logic Elements (LE) (K) 190,240 136,880 91,680 58,900 ALM 760,960 547,520 366,720 235,600 Register 24,140 17,260 13,660 10,510 M10K Memory (Kb) 2,906 2,098 1,448 961 MLAB 1,156 1,045 800 396 Variable-precision DSP Block 2,312 2,090 1,600 792 18 x 18 Multiplier 16 12 12 10 PLL 5 6 (36) 6 (24) 6 (24) 3 (9) 6 Gbps 6 Transceiver 20 12 12 4 10 Gbps 7 704 704 544 416 GPIO 8 160 160 120 68 Transmitter LVDS 176 176 136 80 Receiver 2 2 2 1 PCIe Hard IP Block 4 4 4 2 Hard Memory Controller Related Information High-Speed Differential I/O Interfaces and DPA in Arria V Devices chapter, Arria V Device Handbook Provides the number of LVDS channels in each device package. Transceiver Architecture in Arria V Devices Describes 10 Gbps channels usage conditions. 5 The number of PLLs includes general-purpose fractional PLLs and transceiver fractional PLLs. 6 The 6 Gbps transceiver counts are for dedicated 6-Gbps channels. You can also configure any pair of 10 Gbps channels as three 6 Gbps channels-the total number of 6 Gbps channels are shown in brackets. 7 Chip-to-chip connections only. For 10 Gbps channel usage conditions, refer to the Transceiver Architecture in Arria V Devices chapter. For information about 10 Gbps SFF-8431 compliance, contact Altera. 8 The number of GPIOs does not include transceiver I/Os. In the Quartus II software, the number of user I/Os includes transceiver I/Os. Arria V Device Overview Altera Corporation Feedback AV-51001 Maximum Resources 8 2013.05.06 |
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