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EP2S90F1508C5ES Datasheet(PDF) 6 Page - Altera Corporation |
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EP2S90F1508C5ES Datasheet(HTML) 6 Page - Altera Corporation |
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6 / 238 page  1–4 Altera Corporation Stratix II Device Handbook, Volume 1 May 2007 Features After compilation, check the information messages for a full list of I/O, DQ, LVDS, and other pins that are not available because of the selected migration path. Table 1–4 lists the Stratix II device package offerings and shows the total number of non-migratable user I/O pins when migrating from one density device to a larger density device. Additional I/O pins may not be migratable if migrating from the larger device to the smaller density device. 1 When moving from one density to a larger density, the larger density device may have fewer user I/O pins. The larger device requires more power and ground pins to support the additional logic within the device. Use the Quartus II Pin Planner to determine which user I/O pins are migratable between the two devices. 1 To determine if your user I/O assignments are correct, run the I/O Assignment Analysis command in the Quartus II software (Processing > Start > Start I/O Assignment Analysis). f Refer to the I/O Management chapter in volume 2 of the Quartus II Handbook for more information on pin migration. Table 1–4. Total Number of Non-Migratable I/O Pins for Stratix II Vertical Migration Paths Vertical Migration Path 484-Pin FineLine BGA 672-Pin FineLine BGA 780-Pin FineLine BGA 1020-Pin FineLine BGA 1508-Pin FineLine BGA EP2S15 to EP2S30 0 (1) 0 EP2S15 to EP2S60 8 (1) 0 EP2S30 to EP2S60 8 (1) 8 EP2S60 to EP2S90 0 EP2S60 to EP2S130 0 EP2S60 to EP2S180 0 EP2S90 to EP2S130 0 (1) 16 17 EP2S90 to EP2S180 16 0 EP2S130 to EP2S180 0 0 Note to Table 1–4: (1) Some of the DQ/DQS pins are not migratable. Refer to the Quartus II software information messages for more detailed information. |
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