HI-8599

0

data

data

1

parity bit

0 = odd parity

1= odd parity error (even parity)

CR4

ARINC BUS

FIFO

32nd bit

32nd bit

Error Bit:

FUNCTIONAL DESCRIPTION (cont.)

RECEIVER PARITY

The Receiver Parity Check Enable bit (Control Register bit 4,

CR4) controls how the 32nd bit of the received ARINC word is

interpreted by the HI-3585 receiver.

, the 32nd bit is treated as data and

transferred as received from the ARINC bus to the receive FIFO.

, the 32nd bit is treated as a parity

error bit.

The receiver expects the 32nd bit of the received word to

indicate odd parity. If this is the case, the parity bit is reset to

indicate correct parity was received and resulting word is

written to the receive FIFO.

If the received word is even parity, the receiver sets the 32nd

bit to a “1”, indicating a parity error. The resulting word is then

written to the receive FIFO.

Therefore, when CR4 is set to “1”, the 32nd bit retrieved from the

receiver FIFO will always be “0” when valid (odd parity) ARINC 429

words are received.

When CR4 is set to a “0”

When CR4 is set to a “1”

Odd Parity Received

Even Parity Received

TRANSMITTER

A block diagram of the transmitter section is shown in Figure 3.

The FIFO is loaded sequentially by first pulsing

to load byte 1

and then

to load byte 2. The control logic automatically loads

the 31 bit word in the next available position of the FIFO. If TX/R,

the transmitter ready flag is high (FIFO empty), then 8 words, each

31 bits long, may be loaded. If TX/R is low, then only the available

positions may be loaded. If all 8 positions are full, the FIFO ignores

further attempts to load data.

When ENTX goes high, enabling transmission, the FIFO positions

are incremented with the top register loading into the data

transmission shift register. Within 2.5 data clocks the first data bit

appears at either TXA(OUT) or TXB(OUT). The 31 bits in the data

transmission shift register are presented sequentially to the outputs

in the ARINC 429 format with the following timing:

ARINC DATA BIT TIME

10 Clocks

80 Clocks

DATA BIT TIME

5 Clocks

40 Clocks

NULL BIT TIME

5 Clocks

40 Clocks

WORD GAP TIME

40 Clocks

320 Clocks

The word counter detects when all loaded positions are transmitted

and sets the transmitter ready flag, TX/R, high.

FIFO OPERATION

DATA TRANSMISSION

PL1

PL2

HIGH SPEED

LOW SPEED

TRANSMITTER PARITY

The parity generator counts the ONES in the 31-bit word. If the

BD12 control word bit is set low, the 32nd bit transmitted will

make parity odd. If the control bit is high, the parity is even.

If the BD05 control word bit is set low, the digital outputs of the

transmitter are internally connected to the logic inputs of the

receivers, bypassing the analog bus interface circuitry. Data to

Receiver 1 is as transmitted and data to Receiver 2 is the

complement. All data transmitted during self test is also present

on the TXA(OUT) and TXB(OUT) line driver outputs.

Taking

TEST high forces TXA(OUT) and TXB(OUT) into the null state

regardless of the state of Bd05 control word bit.

The two receivers are independent of the transmitter. Therefore,

control of data exchanges is strictly at the option of the user. The

only restrictions are:

1.

The received data may be overwritten if not retrieved within

one ARINC word cycle.

2.

The FIFO can store 8 words maximum and ignores attempts to

load addition data if full.

3.

Byte 1 of the transmitter data must be loaded first.

4.

Either byte of the received data may be retrieved first. Both

bytes must be retrieved to clear the data ready flag.

5.

After ENTX, transmission enable, goes high it cannot go low

until TX/R, transmitter ready flag, goes high. Otherwise, one

ARINC word is lost during transmission.

SELF TEST

SYSTEM OPERATION

HOLT INTEGRATED CIRCUITS

5