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5AGXMB1D631I4N Datasheet(PDF) 10 Page - Altera Corporation |
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5AGXMB1D631I4N Datasheet(HTML) 10 Page - Altera Corporation |
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10 / 82 page  1–4 Chapter 1: Overview for the Arria V Device Family Arria V Family Plan Arria V Device Handbook February 2012 Altera Corporation Volume 1: Device Overview and Datasheet Arria V Family Plan Arria V devices offer various thermal composite flip chip BGA packaging options with differing price and performance points. Table 1–2 and Table 1–3 list the Arria V devices features. Configuration ■ Partial and dynamic reconfigurations ■ CvP ■ Configuration via HPS ■ Serial and parallel flash interface ■ Enhanced advanced encryption standard (AES) design security features ■ Tamper protection ■ Remote system upgrade Packaging ■ Thermal composite flip chip BGA packaging ■ Multiple device densities with identical package footprints for seamless migration between different device densities ■ Lead, lead-free (Pb-free), and RoHS-compliant options Table 1–1. Feature Summary for Arria V Devices (Part 3 of 3) Feature Details Table 1–2. Maximum Resource Counts for Arria V GX Devices —Preliminary Feature Arria V GX Device 5AGXA1 5AGXA3 5AGXA5 5AGXA7 5AGXB1 5AGXB3 5AGXB5 5AGXB7 ALMs 28,302 56,100 71,698 91,680 113,208 136,880 158,491 190,240 LE (K) 75 148 190 242 300 362 420 504 M10K memory blocks 800 1,051 1,180 1,366 1,510 1,726 2,054 2,414 MLAB memory (Kbit) 463 873 1,173 1,448 1,852 2,098 2,532 2,906 Block memory (Kbit) 8,000 10,510 11,800 13,660 15,100 17,260 20,540 24,140 Variable-precision DSP blocks 240 396 600 800 920 1,045 1,092 1,139 18 x 19 multipliers 480 792 1,200 1,600 1,840 2,090 2,184 2,278 Fractional PLLs (1) 10 10 12 12 12 12 16 16 GPIO 480 480 544 544 704 704 704 704 LVDS transmitter (TX) (2) 68 68 120 120 160 160 156 160 LVDS receiver (RX) (2) 80 80 136 136 176 176 172 176 PCIe hard IP blocks 1 1 2 2 2 2 2 2 Hard memory controllers 2 2 4 4 4 4 4 4 Notes to Table 1–2: (1) The total number of available fractional PLLs is a combination of general-purpose and transceiver PLLs. Transceiver fractional PLLs that are not used by the transceiver I/O can be used as general-purpose fractional PLLs. (2) For the LVDS channels count for each package, refer to the High-Speed Differential I/O Interfaces with DPA in Arria V Devices chapter. |
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