 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
HI-3586PQI Datasheet(PDF) 10 Page - Holt Integrated Circuits |
|
||||||||||||||||||||||||||||||
HI-3586PQI Datasheet(HTML) 10 Page - Holt Integrated Circuits |
|
|
10 / 19 page  MSB LSB MSB LSB High Z High Z CS SO SI 01234567 SCK (SPI Mode 0) Figure 4. Generalized Single-Byte Transfer Using SPI Protocol Mode 0 SERIAL PERIPHERAL INTERFACE (SPI) BASICS The HI-3585 uses an SPI synchronous serial interface for host access to internal registers and data FIFOs. Host serial communication is enabled through the Chip Select ( ) pin, and is accessed via a three-wire interface consisting of Serial Data Input (SI) from the host, Serial Data Output (SO) to the host and Serial Clock (SCK). All read / write cycles are completely self- timed. The SPI (Serial Peripheral Interface) protocol specifies master and slave operation; the HI-3585 operates as an SPI slave. The SPI protocol defines two parameters, CPOL (clock polarity) and CPHA (clock phase). The possible CPOL-CPHA combinations define four possible "SPI Modes". Without describing details of the SPI modes, the HI-3585 operates in mode 0 where input data for each device (master and slave) is clocked on the rising edge of SCK, and output data for each device changes on the falling edge (CPHA = 0, CPOL = 0). Be sure to set the host SPI logic for mode 0. As seen in Figure 4, SPI Mode 0 holds SCK in the low state when idle. The SPI protocol transfers serial data as 8-bit bytes. Once chip select is asserted, the next 8 rising edges on SCK latch input data into the master and slave devices, starting with each byte’s most-significant bit. Multiple bytes may be transferred when the host holds low after the first byte transferred, and continues to clock SCK in multiples of 8 clocks. A rising edge on chip select terminates the serial transfer and reinitializes the HI-3585 SPI for the next transfer. If goes high before a full byte is clocked by SCK, the incomplete byte clocked into the device SI pin is discarded. In the general case, both master and slave simultaneously send and receive serial data (full duplex), per Figure 4 below. However the HI-3585 operates half duplex, maintaining high impedance on the SO output, except when actually transmitting serial data. When the HI-3110 is sending data on SO during read operations, activity on its SI input is ignored. Figures 5 and 6 show actual behavior for the HI-3585 SO output. CS CS CS CS CS SERIAL PERIPHERAL INTERFACE HOLT INTEGRATED CIRCUITS 10 HI-3585, HI-3586 |
Similar Part No. - HI-3586PQI |
|
Similar Description - HI-3586PQI |
|
|
|
Link URL |
| Privacy Policy |
| ALLDATASHEET.NET |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
