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HI-3585PCIF Datasheet(PDF) 11 Page - Holt Integrated Circuits |
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HI-3585PCIF Datasheet(HTML) 11 Page - Holt Integrated Circuits |
11 / 19 page Figure 6. 2-Byte Write example CS SO SI SCK SPI Mode 0 MSB LSB 0 12 3 4 5 67 High Z 0 12 3 4 5 67 0 12 3 4 5 67 MSB LSB MSB LSB Data Byte 0 Data Byte 1 Op-Code Byte Host may continue to assert here to write sequential byte(s) when allowed by the SPI instruction. Each byte needs 8 SCK clocks. CS Figure 5. Single-Byte Read From a Register CS SO SI SCK MSB LSB 0 12 3 4 5 67 High Z High Z 0 12 3 4 5 67 MSB LSB MSB LSB Data Byte Op-Code Byte Host may continue to assert here to read sequential word(s) when allowed by the instruction. Each word needs 8 SCK clocks. CS HI-3585 SPI COMMANDS For the HI-3585, each SPI read or write operation begins with an 8-bit command byte transferred from the host to the device after assertion of . Since HI-3585 command byte reception is half- duplex, the host discards the dummy byte it receives while serially transmitting the command byte. Figures 5 and 6 show read and write timing as it appears for a single-byte and dual-byte register operation. The command byte is immediately followed by a data byte comprising the 8-bit data word read or written. For a single register read or write, is negated after the data byte is transferred. Multiple byte read or write cycles may be performed by transferring more than one byte before is negated. Table 1 defines the required number of bytes for each instruction. Note: SPI Instruction op-codes not shown in Tables 1 are “reserved” and must not be used. Further, these op-codes will not provide meaningful data in response to read commands. ; must be negated after the command, then reasserted for the following Read or Write command. CS CS CS CS Two instruction bytes cannot be “chained” HOST SERIAL PERIPHERAL INTERFACE (cont.) HOLT INTEGRATED CIRCUITS 11 HI-3585, HI-3586 |
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