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HI-8591CRMF-40 Datasheet(PDF) 2 Page - Holt Integrated Circuits |
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HI-8591CRMF-40 Datasheet(HTML) 2 Page - Holt Integrated Circuits |
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2 / 8 page  HI-8591 FUNCTIONAL DESCRIPTION RECEIVER Figure 1 shows the general architecture of the ARINC 429 receiver. The receiver operates off the VCC supply only. The inputs RINA and RINB each require 140K of resis- tance between the ARINC bus and comparator. This resis- tance is completely on-chip for the HI-8591. In contrast, the HI-8591-40 has 100 K on-chip and requires an exter- nal 40K , ¼ watt resistor on each of the ARINC 429 input pins. The HI-8591-40 device is typically chosen for appli- cations where lightning protection is a requirement. After level translation, the inputs are buffered and become inputs to a differential amplifier. The amplitude of the differ- ential signal is compared to levels derived from a divider between VCC and Ground. The nominal settings corre- W W W spond to a One/Zero amplitude of 6.0V and a Null ampli- tude of 3.3V. The status of the ARINC receiver input is latched. A Null input resets the latches and a One or Zero input sets the latches. The logic at the output is controlled by the test signal which is generated by the logical OR of the TESTA and TESTB pins. If TESTA and TESTB are both One, the HI- 8591 outputs are pulled low. This allows the digital out- puts of a transmitter to be connected to the test inputs through control logic for system self-test purposes. TXBOUT TXAOUT TX1IN TX0IN ARINC Channel RINB RINA TESTA TESTB { HARDWIRE OR DRIVE FROM LOGIC ROUTB ROUTA 3.3V VCC V- -15V GND TXD0 TXD1 RXD0 RXD1 FPGA ARINC Channel 1 2 8 6 7 4 3 4 5 6 7 2 3 HI-8591 APPLICATION INFORMATION 15V V+ 8 5 HI-8586 SLP1.5 1 Figure 2 shows a possible application of the HI-8591 interfacing an ARINC 429 bus input to a 3.3V ASIC or FPGA. In this example a HI-8586 ARINC 429 line driver is used to take 3.3V logic outputs and generate the nec- essary 10V differential signal for driving an ARINC 429 bus. GND FIGURE 2 - APPLICATION DIAGRAM TEST RINA RINB NULL ZERO NULL ONE TESTA ROUTB ROUTA FIGURE 1 - RECEIVER BLOCK DIAGRAM SQ R LATCH ESD PROTECTION AND TRANSLATION LATCH SQ TESTB R TESTA TESTB TEST HOLT INTEGRATED CIRCUITS 2 |
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