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LMP92064 Datasheet(PDF) 3 Page - Texas Instruments |
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LMP92064 Datasheet(HTML) 3 Page - Texas Instruments |
3 / 23 page SDI SDO DAP DGND VDIG 5 6 7 8 INVP INVG GND VDD 12 11 10 9 1 2 3 4 REFC REFG INCP INCN 16 15 14 13 RESET RESERVED CSB SCLK LMP92064 www.ti.com SNOSCX0 – JUNE 2013 CONNECTION DIAGRAM Figure 2. Top View WSON-16 Package Table 1. Pin Descriptions PIN I/O(1) DESCRIPTION NAME NO. 1 REFC n/a Internal reference bypass capacitor pin 2 REFG G Internal reference ground 3 INCP I Positive current channel input 4 INCN I Negative current channel input 5 INVP I Positive voltage channel input 6 INVG G Ground reference for the negative voltage channel input 7 GND G Analog ground 8 VDD P Analog power supply 9 VDIG P Digital power supply 10 DGND G Digital ground 11 SDO O SPI Bus push-pull serial data digital output 12 SDI I SPI Bus serial data digital input 13 SCLK I SPI Bus clock digital input 14 CSB I SPI Bus chip select bar digital input 15 RESERVED n/a Reserved (Do not connect) 16 RESET I Reset (high-active) n/a DAP n/a No connection (Do not connect) (1) G = Ground, I = Input, O = Output, P = Power Copyright © 2013, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: LMP92064 |
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