The HI-3588 accepts signals within these tolerances and rejects

signals outside these tolerances. Receiver logic achieves this as

described below:

1. An accurate 1MHz clock source is required to validate the

receive signal timing. Less than 1% error is recommended.

2. The receiver uses three separate 10-bit sampling shift reg-

isters for Ones detection, Zeros detection and Null detection.

When the input signal is within the differential voltage range

for any shift register’s state (One Zero or Null) sampling

clocks a high bit into that register. When the receive signal is

outside the differential voltage range defined for any shift reg-

ister, a low bit is clocked. Only one shift register can clock a

high bit for any given sample. All three registers clock low

bits if the differential input voltage is between defined state

voltage bands.

Valid data bits require at least three consecutive One or Zero

samples (three high bits) in the upper half of the Ones or Ze-

ros sampling shift register, and at least three consecutive Null

samples (three high bits) in the lower half of the Null sampling

shift register within the data bit interval.

A word gap Null requires at least three consecutive Null sam-

ples (three high bits) in the upper half of the Null sampling

shift register and at least three consecutive Null samples

(three high bits) in the lower half of the Null sampling shift reg-

ister. This guarantees the minimum pulse width.

3. To validate the receive data bit rate, each bit must follow

its preceding bit by not less than 8 samples and not more

than 12 samples. With exactly 1MHz input clock frequency,

the acceptable data bit rates are:

83K BPS

10.4K BPS

125K BPS

15.6K BPS

4. Following the last data bit of a valid reception, the Word

Gap timer samples the Null shift register every 10 input

clocks (every 80 clocks for low speed). If a Null is present,

the Word Gap counter is incremented. A Word Gap count of 3

enables the next reception.

DATA BIT RATE MIN

DATA BIT RATE MAX

HIGH SPEED

LOW SPEED

FUNCTIONAL DESCRIPTION (cont.)

HI-3588

The HI-3588 guarantees recognition of these levels with a common

mode voltage with respect to GND less than ±30V for the worst case

condition (3.15V supply and 13V signal level). Design tolerances

guarantee detection of the above levels, so the actual acceptance

ranges are slightly larger. If the ARINC signal (including nulls) is

outside the differential voltage ranges, the HI-3588 receiver rejects

the data.

Figure 2 is a block diagram showing receiver logic.

The ARINC 429 specification defines the following timing toler-

ances for received data:

100K BPS ± 1%

12K -14.5K BPS

1.5 ± 0.5 µsec

10 ± 5 µsec

1.5 ± 0.5 µsec

10 ± 5 µsec

5 µsec ± 5%

34.5 to 41.7 µsec

RECEIVER LOGIC OPERATION

BIT TIMING

BIT RATE

PULSE RISE TIME

PULSE FALL TIME

PULSE WIDTH

HIGH SPEED

LOW SPEED

ARINC 429 RECEIVER

ARINC BUS INTERFACE

Figure 1 shows the input circuit for the ARINC 429 line receiver. The

ARINC 429 specification requires the following detection levels:

ONE

+6.5 Volts to +13 Volts

NULL

+2.5 Volts to -2.5 Volts

ZERO

-6.5 Volts to -13 Volts

STATE

DIFFERENTIAL VOLTAGE

DIFFERENTIAL

AMPLIFIERS

COMPARATORS

FIGURE 1. ARINC RECEIVER INPUT

RINA-40

RINA

RINB

RINB-40

VDD

GND

VDD

GND

ONE

NULL

ZERO

HOLT INTEGRATED CIRCUITS

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