AC ELECTRICAL CHARACTERISTICS

HI-3588

VDD = 3.3V or 5.0V, GND = 0V, TA = Operating Temperature Range and fclk=1MHz 0.1% with 60/40 duty cycle

+

HOLT INTEGRATED CIRCUITS

10

LIMITS

PARAMETER

SYMBOL

UNITS

MIN

TYP

MAX

SPI INTERFACE TIMING - 5.0V

RECEIVER TIMING

SCK clock period

active after last SCK rising edge

t

10

ns

setup time to first SCK rising edge

t

10

ns

hold time after last SCK falling edge

t

40

ns

inactive between SPI instructions

t

Delay - Last bit of received ARINC word to RFLAG(Full or Empty) - Hi Speed

t

16

µs

Received data available to SPI interface. RFLAG to

active

SPI receiver read or clear FIFO instruction to RFLAG

t

t

250

ns

20

ns

SPI SI Data set-up time to SCK rising edge

t

25

ns

SPI SI Data hold time after SCK rising edge

t

15

ns

SCK rise time

t

10

ns

SCK fall ime

t

10

ns

SO valid after SCK falling edge

t

125

ns

SO high-impedance after SCK falling edge

t

100

ns

Master Reset pulse width

t

150

ns

SCK clock period

t

390

ns

active after last SCK rising edge

t

10

ns

setup time to first SCK rising edge

t

10

ns

hold time after last SCK falling edge

t

40

ns

inactive between SPI instructions

t

35

ns

SPI SI Data set-up time to SCK rising edge

t

30

ns

SPI SI Data hold time after SCK rising edge

t

30

ns

SCK rise time

t

10

ns

SCK fall ime

t

10

ns

SO valid after SCK falling edge

t

195

ns

SO high-impedance after SCK falling edge

t

100

ns

Master Reset pulse width

t

150

ns

Delay - Last bit of received ARINC word to RFLAG(Full or Empty) - Lo Speed

t

126

µs

t0

ns

155

ns

CYC

CPH

DS

DH

SCKR

SCKF

DV

CHZ

CYC

CHH

CES

CEH

CPH

DS

DH

SCKR

SCKF

DV

CHZ

RFLG

RXR

CS

CS

CS

CS

CS

CHH

CES

CEH

RFLG

SPIF

MR

MR

SPI INTERFACE TIMING - 3.3V

CS

CS

CS

CS