FUNCTIONAL DESCRIPTION

DATA

BUS

FUNCTION

CONTROL

DESCRIPTION

PIN

If enabled, an internal connection

BDO5

SELF TEST

0 = ENABLE

is made passing 429DO and

to the receiver logic inputs

RECEIVER 1

If enabled, ARINC bits 9 and,

BDO6

DECODER

1 = ENABLE

10 must match the next two

control word bits

If Receiver 1 Decoder is

BDO7

-

-

enabled, the ARINC bit 9

must match this bit

If Receiver 1 Decoder is

BDO8

-

-

enabled, the ARINC bit 10

must match this bit

RECEIVER 2

If enabled, ARINC bits 9 and

BDO9

DECODER

1 = ENABLE

10 must match the next two

control word bits

If Receiver 2 Decoder is

BD10

-

-

enabled, then ARINC bit 9

must match this bit

If Receiver 2 Decoder is

BD11

-

-

enabled, then ARINC bit 10

must match this bit

INVERT

Logic 0 enables normal odd parity

BD12

XMTR

1 = ENABLE

and Logic 1 enables even parity

PARITY

output in transmitter 32nd bit

BD13

XMTR DATA

0 = ÷10

CLK is divided either by 10 or

CLK SELECT

1 = ÷80

80 to obtain XMTR data clock

BD14

RCVR DTA

0 = ÷10

CLK is divided either by 10 or

CLK SELECT

1 = ÷80

80 to obtain RCVR data clock

429DO

CONTROL WORD REGISTER

The HI-8282A contains 10 data flip flops whose D inputs are con-

nected to the data bus and clocks connected to

. Each

flip flop provides options to the user as follows:

CWSTR

THE RECEIVERS

ARINC BUS INTERFACE

Figure 1 shows the input circuit for each receiver. The ARINC 429

specification requires the following detection levels:

The HI-8282A guarantees recognition of these levels with a common

mode Voltage with respect to GND less than ±5V for the worst case

condition (4.75V supply and 13v signal level).

Design tolerances guarantee detection of the above levels, so the

actual acceptance ranges are slightly larger. If the ARINC signal is

out of the actual acceptance ranges, including the nulls, the chip

rejects the data.

STATE

DIFFERENTIAL VOLTAGE

ONE

+6.5 Volts to +13 Volts

NULL

+2.5 Volts to -2.5 Volts

ZERO

-6.5 Volts to -13 Volts

HI-8282A-10

The HI-8282A-10 option is similar to the HI-8282A with the exception

that it allows an external 10K to 15K ohm resistor to be added in

series with each ARINC input without affecting the ARINC input

thresholds. This option is especially useful in applications where

lightning protection circuitry is also required.

Each side of the ARINC bus must be connected through a 10K to 15K

ohm series resistor in order for the chip to detect the correct ARINC

levels. The typical 10 volt differential signal is translated and input to

a window comparator and latch. The comparator levels are set so

that with the external 10K to 15K ohm resistors, they are just below

the standard 6.5 V minimum ARINC data threshold and just above

the 2.5 V maximum ARINC null threshold.

The receivers of the HI-8282A-10, when used with external

15K ohm resistors, will withstand DO-160F, Level 3, waveforms 3,

4, 5A and 5B pin injection. No additional lightning protection circuit

is necessary.

Please refer to the Holt AN-300 Application Note for additional

information and recommendations on lightning protection of Holt

Line Drivers and Receivers.

GND

GND

429DI1(B)

OR

429DI2(B)

429DI1(A)

OR

429DI2(A)

DIFFERENTIAL

AMPLIFIERS

ONES

COMPARATORS

NULL

ZEROES

FIGURE 1. ARINC RECEIVER INPUT

ARINC 429 DATA FORMAT

The following table shows the bit positions in exchanging data with the

receiver or transmitter.

ARINC bit 1 is the first bit transmitted or

received.

DATA

BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD

BUS

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

00

ARINC

13

12

11

10

9

31

30

32

12345678

BIT

BYTE 1

BYTE 2

DATA

BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD

BUS

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

00

ARINC

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

BIT

HI-8282A

HOLT INTEGRATED CIRCUITS

3