HOLT INTEGRATED CIRCUITS

7

HI-3593

Bit Name

7-6 R2INT[1:0]

5-4 R2FLAG[1:0]

1-0 R1FLAG[1:0]

R/W

R/W

Default

Description

R/W

0

The value of R2INT[1:0] defines the function of the R2INT output pin, as follows:

00

R2INT pulses high when a valid message is received and

placed in the Receiver 2 FIFO or any of the Receiver 2 Priority-

Label mail boxes

01

R2INT pulses high when a message is received in Receiver 2

Priority-Label mail box #1

10

R2INT pulses high when a message is received in Receiver 2

Priority-Label mail box #2

11

R2INT pulses high when a message is received in Receiver 2

Priority-Label mail box #3

R/W

0

The value of R2FLAG[1:0] defines the function of the R2FLAG output pin, as follows:

00

R2FLAG goes high when Receiver 2 FIFO is empty

01

R2FLAG goes high when Receiver 2 FIFO contains 32 ARINC

429 words (FIFO is full)

10

R2FLAG goes high when Receiver 2 FIFO contains at least

sixteen ARINC 429 words (FIFO is half-full)

11

R2FLAG goes high when Receiver 2 FIFO contains one or more

words (FIFO is not empty)

3-2 R1INT[1:0]

R/W

0

The value of R1INT[1:0] defines the function of the R1INT output pin, as follows:

00

R1INT pulses high when a valid message is received and

placed in the Receiver 1 FIFO or any of the Receiver 1 Priority-

Label mail boxes

01

R1INT pulses high when a message is received in Receiver 1

Priority-Label mail box #1

10

R1INT pulses high when a message is received in Receiver 1

Priority-Label mail box #2

11

R1INT pulses high when a message is received in Receiver 1

Priority-Label mail box #3

0

The value of R1FLAG[1:0] defines the function of the R1FLAG output pin, as follows:

00

R1FLAG goes high when Receiver 1 FIFO is empty

01

R1FLAG goes high when Receiver 1 FIFO contains 32 ARINC

429 words (FIFO is full)

10

R1FLAG goes high when Receiver 1 FIFO contains at least

sixteen ARINC 429 words (FIFO is half-full)

11

R1FLAG goes high when Receiver 1 FIFO contains one or more

words (FIFO is not empty)

76543210

MSB

LSB

FLAG / INTERRUPT ASSIGNMENT REGISTER

(Write, SPI Op-code 0x34)

(Read, SPI Op-code 0xD0)