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HI-3597PSIF-40 Datasheet(PDF) 5 Page - Holt Integrated Circuits |
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HI-3597PSIF-40 Datasheet(HTML) 5 Page - Holt Integrated Circuits |
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5 / 18 page  HI-3596, HI-3597, HI-3598, HI-3599 HOLT INTEGRATED CIRCUITS 5 FUNCTIONAL DESCRIPTION Control Word Register Each HI-359x receive channel is assigned a 16-bit Control Register which configures that receiver. Con- trol Register bits CR15 - CR0 are loaded from a 16-bit data value appended to SPI instruction n4 hex, where “n”isthechannelnumber1-8hex.WritingtotheCon- trol Register also clears the data FIFO for that channel. The Control Register contents may be read using SPI instruction n5 hex. Table 3 summarizes the Control Reg- ister bits functions. Table 3. Control Register Bits Functions CR Bit Function State Description CR0 (LSB) Receiver Data Rate Select 0 Data rate = ACLK/10 (ARINC 429 High-Speed) 1 Data rate = ACLK/80 (ARINC 429 Low-Speed) CR1 RFLAG Definition 0 FLAG goes high when receive FIFO is not empty (Contains at least one word) 1 FLAG goes high when receive FIFO is full CR2 Enable Label Recognition 0 Label recognition disabled 1 Label recognition enabled CR3 Reset Receiver 0 Normal Operation 1 Reset this receiver (Clear receiver logic and FIFO). The receive channel is disabled if CR3 is left high CR4 Receiver ParityCheck Enable 0 Receiverparitycheckdisabled 1 Receiveroddparitycheckenabled CR5 Self-Test (Loopback) 0 Receiver’sinputsareconnectedtothe Transmit Register serial data output. 1 Normal operation CR6 Receiver Decoder 0 Receiver Decoder Disabled 1 ARINC bits 10 and 9 must match CR7 and CR8 CR7 - - If receiver decoder is enabled, the ARINC bit 10 must match this bit CR8 - - If receiver decoder is enabled, the ARINC bit 9 must match this bit CR9 ARINC Label Bit Order 0 Label bit order reversed (See Table 5) 1 Label bit order same as received (See Table 5) CR10 to CR15 (MSB) Not Used X Controlregisterreadreturns“0”for these bits Status Register The HI-359x devices have a single 16-bit Status Reg- ister which is read to determine status for the eight received data FIFOs. The Status Register is read using SPI instruction n6 hex. Table 4 summarizes the Status Register bits functions. Table 4. Status Register Bits Functions CR Bit Function State Description SR0 (LSB) Receiver 1 FIFO Empty 0 Receiver 1 FIFO contains valid data. Resets to Zero when all data has been read.FLAGpinreflectsthestateof thisbitwhenCR1=”0” 1 Receiver 1 FIFO is empty SR1 Receiver 2 FIFO Empty 0 Receiver 2 FIFO contains valid data. 1 Receiver 2 FIFO is empty SR2 to SR6 Receiver 3 to Receiver 7 FIFO Empty : : : : : : : : SR7 Receiver 8 FIFO Empty 0 Receiver 8 FIFO contains valid data. 1 Receiver 8 FIFO is empty SR8 Receiver 1 FIFO Full 0 Receiver 1 FIFO not full. FLAG pin reflectsthestateofthisbitwhen CR1=”1” 1 Receiver 1 FIFO full. To avoid data loss, the FIFO must be read within one ARINC word period. SR9 Receiver 2 FIFO Full 0 Receiver 2 FIFO not full. 1 Receiver 2 FIFO full. SR10 to SR14 Receiver 3 to Receiver 7 FIFO Full : : : : : : : : SR15 (MSB) Receiver 8 FIFO Full 0 Receiver 8 FIFO not full. 1 Receiver 8 FIFO full. |
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