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HI-8589 Datasheet(PDF) 4 Page - Holt Integrated Circuits |
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HI-8589 Datasheet(HTML) 4 Page - Holt Integrated Circuits |
4 / 15 page FUNCTIONAL DESCRIPTION (cont.) HI-8581, HI-8589 SEL EN D/R DECODER CONTROL BITS / MUX CONTROL LATCH ENABLE CONTROL 32 TO 16 DRIVER 32 BIT LATCH 32 BIT SHIFT REGISTER TO PINS CONTROL BIT BD14 CLOCK OPTION CLOCK CLK BIT COUNTER AND END OF SEQUENCE PARITY CHECK 32ND BIT DATA BIT CLOCK EOS WORD GAP WORD GAP TIMER BIT CLOCK END START SEQUENCE CONTROL ERROR CLOCK ERROR DETECTION SHIFT REGISTER SHIFT REGISTER NULL ZEROS SHIFT REGISTER ONES EOS BITS9&10 FIGURE 2. RECEIVER BLOCK DIAGRAM RECEIVER LOGIC OPERATION BIT TIMING BIT RATE PULSE RISE TIME PULSE FALL TIME PULSE WIDTH Figure 2 is a block diagram showing each receiver’s logic. ARINC 429 specifies the following timing for received data: 100K BPS ± 1% 12K -14.5K BPS 1.5 ± 0.5 µsec 10 ± 5 µsec 1.5 ± 0.5 µsec 10 ± 5 µsec 5 µsec ± 5% 34.5 - 41.7 µsec The HI-8581 and HI-8589 accepts signals meeting these specifi- cations and rejects signals outside these tolerances using the method described here: 1. The timing logic requires an accurate 1.0 MHz clock source. Less than 0.1% error is recommended. 2. The sampling shift registers are 10 bits long and must show three consecutive Ones, Zeros or Nulls to be consid- ered valid data. To qualify data bits, One or Zero in the upper bits of the sampling shift register must be followed by Null in the lower bits within the data bit time. A word gap Null re- quires three consecutive Nulls in both the upper and lower bits of the sampling shift register. This guarantees the mini- mum pulse width. HIGH SPEED LOW SPEED 3. Each data bit must follow its predecessor by not less than 8 samples and not more than 12 samples. In this manner the bit rate is checked. With exactly 1 MHz input clock frequency, the acceptable data bit rates are as follows: 83K BPS 10.4K BPS 125K BPS 15.6K BPS DATA BIT RATE MIN DATA BIT RATE MAX HIGH SPEED LOW SPEED 4. The Word Gap timer samples the Null shift register every 10 input clocks (80 for low speed) after the last data bit of a valid reception. If the Null is present, the Word Gap counter is incremented. A count of 3 enables the next reception. The 32nd bit of received ARINC words stored in the receive FIFO is used as a Parity Flag indicating whether good Odd parity is re- ceived from the incoming ARINC word. The parity bit is reset to indicate correct parity was received and the resulting word is then written to the receive FIFO. The receiver sets the 32nd bit to a “1”, indicating a parity error and the resulting word is then written to the receive FIFO. Therefore, the 32nd bit retrieved from the receiver FIFO will al- ways be a “0” when valid (odd parity) ARINC 429 words are re- ceived. Once 32 valid bits are recognized, the receiver logic generates an End of Sequence (EOS). If the receiver decoder is enabled and the 9th and 10th ARINC bits match the control word program bits or if the receiver decoder is disabled, then EOS clocks the data ready flag flip flop to a "1", or (or both) will go low. The data flag for a receiver remains low until after ARINC bytes from that receiver are retrieved. This is accomplished by first acti- vating with SEL, the byte selector, low to retrieve the first byte and then activating with SEL high to retrieve the second byte. retrieves data from receiver 1 and retrieves data from re- ceiver 2. If another ARINC word is received and a new EOS occurs before the two bytes are retrieved, the data is overwritten by the new word. RECEIVER PARITY Odd Parity Received Even Parity Received RETRIEVING DATA D/R1 D/R2 EN EN EN1 EN2 both HOLT INTEGRATED CIRCUITS 4 |
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